There is no checkoff for lab this week. This is primarily review for the midterm, this will cover only a subset of the material in scope and is not a representation of what will appear on the exam.
Recall that the critical path is the longest path (delay) from register to register, whether it be the same or different register. Setup time is the amount of time before the clock rise that the input signal must remain constant. Clock-to-Q time is the amount of time after the clock rise that the output signal takes to reflect the saved value. Hold time is the amount of time after the clock rise that the input signal must remain constant.
Some general formulas to note:
critical path = clk-to-q + LONGEST CL + setup
maximum hold time <= clk-to-q + SHORTEST CL
Special note for those of you who bothered to read this: The idea of “maximum hold time” has been a little confused in this class, so we won’t be focusing on it in Midterm 2 for Summer 2019.
Make sure you know the different control signals, what they do, and how they affect our datapath!
rs1 == rs2
rs1 < rs2
based off of BrUnRecall that pipelining involves adding registers in between operations to create checkpoints in our datapath.
Latency is defined as how long it takes for one instruction to finish to completion. Bandwidth is defined as how many instructions you can complete in a specified amount of time.
When we pipeline a circuit, does latency generally go up or down? What about bandwidth?
Cache questions can be particularly tricky to those who don’t know how to approach them, so we’ll break down the approach!
Given the following scenario:
2 KiB Direct-mapped cache, with 128 B blocks and 4 MiB address space, what are the values for the following:
(Hint: # addr = # tag + # index + # offset)
Now, given the following chunk of code, answer the following (you may assume that integers are 4 bytes):
int arr[1024]; // 2^10 Integers
for (int i = 0; i < 1024; i += 4) {
arr[i] = 0; // Line 1
}
for (in i = 1023; i >= 0; i -= 8) {
arr[i] += i; // Line 2
}
You should note the following:
For multi-access patterns such as this, where Line 2 operates after Line 1, we know that Line 2 doesn’t operate on a cold cache, so we need to see if the contents of the cache at the beginning of the loop affect Line 2. Hopefully you understand why the second half of the array is in the cache when we start Line 2, and that Line 2 starts with the second half of the array. Thus, ask yourself what the hit rate of Line 2 must be for the first half of the iterations!
Next, try to answer the rest using our tactics described to answer the original questions.
Good luck on the midterm!