1 |
6/21 |
Intro, Number Representation
|
Course Policies
|
Lab 0: Intro and Setup
Due 6/24
|
Homework 1: Number Rep
Due 6/25
|
6/22 |
C Intro
|
K&R Ch. 1-5 C Reference Slides
Brian Harvey's Intro to C
|
|
|
6/23 |
C Arrays, Pointers, Strings
|
K&R 5-6
|
Discussion 1: Number Rep
|
Homework 2: C Concepts
Due 6/29
|
6/24 |
C Memory Management, Usage
|
K&R 7.8.5, 8.7
|
Lab 1: C and GDB
Due 6/29
|
|
6/25 |
|
|
Discussion 2: C Basics
|
Project 1: Philphix
Due 7/02
|
2 |
6/28 |
Floating Point
|
P&H 3.5, 3.9
IEEE 754 Simulator
|
|
|
6/29 |
RISC-V Intro, `lw`, `sw`, Decisions
|
P&H 2.1-2.3, 2.9-2.10
|
Lab 2: Advanced C and Valgrind
Due 7/01
|
Homework 3: Floating Point
Due 7/02
|
6/30 |
RISC-V Decisions, Procedures
|
P&H 2.6-2.8, 3.2
|
Discussion 3: Floating Point
|
Homework 4: RISC-V
Due 7/06
|
7/1 |
RISC-V Instruction Formats
|
P&H 2.5, 2.10
|
Lab 3: RISC-V Assembly
Due 7/06
|
|
7/2 |
|
|
Discussion 4: RISC-V Intro, Control Flow, ISA
|
Project 2: CS61Classify
A: Due 7/08
B: Due 7/14
|
3 |
7/5 |
No lecture: Holiday
|
|
|
|
7/6 |
Compiler, Assembler, Linker, Loader (CALL)
|
P&H 2.12
|
Lab 4: RISC-V Functions, Pointers
Due 7/09
|
Homework 5: Logic, Timing
Due 7/13
|
7/7 |
Sequential Digital Logic
|
SDS Handout
|
Discussion 5: RISC-V Procedures, CALL
|
|
7/8 |
Combinational Digital Logic
|
|
Lab 5: Logisim
Due 7/15
|
|
7/9 |
|
|
Discussion 6: SDS, Logic, FSMs
|
|
4 |
7/12 |
RISC-V Datapath, Single-Cycle Control Intro
|
P&H 4.1, 4.3
|
|
Homework 6: RISC-V Datapath
Due 7/17
|
7/13 |
RISC-V Single-Cycle Control
|
P&H 4.4
|
|
|
7/14 |
RISC-V 5-Stage Pipeline/Hazards
|
P&H 4.6-4.10
|
Discussion 7: Single-Cycle Datapath
|
Project 3: CS61CPU
A: Due 7/19
B: Due 7/29
|
7/15 |
Caches I
|
P&H 5.1-5.4, 5.8-5.9, 5.13
Cache Flowchart
|
Lab 6: Pipelining, CPU
Due 7/19
|
|
7/16 |
|
|
Discussion 8: Pipelining and Hazards
|
|
5 |
7/19 |
Caches II
|
P&H 5.1-5.4, 5.8-5.9, 5.13
Cache Flowchart
|
|
Homework 7: Caches
Due 7/24
|
7/20 |
Caches III
|
P&H 5.1-5.4, 5.8-5.9, 5.13
Cache Flowchart
|
|
|
7/21 |
No lecture: Midterm study time
|
|
|
|
7/22 |
Midterm
|
|
Lab 7: Caches
Due 7/26
|
|
7/23 |
|
|
Discussion 9: Caches
|
|
6 |
7/26 |
Flynn's Taxonomy, Data-Level Parallelism
|
P&H 2.11, 4.10, 5.10, 6.5
|
Lab 8: Data-Level Parallelism
Due 7/30
|
Homework 8: Performance Programming, Dependability
Due 7/30
|
7/27 |
Thread-Level Parallelism I
|
P&H 2.11, 4.10, 5.10, 6.5
OpenMP Summary Card
|
|
|
7/28 |
Thread-Level Parallelism II
|
P&H 2.11, 4.10, 5.10, 6.5
OpenMP Summary Card
|
Discussion 10: AMAT, Data-Level Parallelism
|
Homework 9: ECC, Parity, Potpourri
Due 8/03
|
7/29 |
Dependability: Parity, ECC, RAID
|
P&H 5.2, 5.5, 5.11
|
Lab 9: Thread-Level Parallelism
Due 8/02
|
Project 4: Numc
Due 8/08
|
7/30 |
|
|
Discussion 11: Coherency, Atomics, Parallellism, ECC & RAID
|
|
7 |
8/2 |
Operating Systems, Virtual Memory
|
P&H 5.7, 5.8
|
|
Homework 10: Virtual Memory
Due 8/06
|
8/3 |
Virtual Memory
|
P&H 5.7, 5.8
|
|
|
8/4 |
I/O
|
P&H 5.2, 5.5, 5.11, A64-B66
|
|
Homework 11: I/O, OS
Due 8/10
|
8/5 |
Summary, What's Next?
|
|
Lab 10: OS, Virtual Memory
Due 8/09
|
|
8/6 |
|
|
Discussion 12: Virtual Memory
|
|
8 |
8/9 |
No lecture: Final study time
|
|
Discussion 13: I/O, OS
|
|
8/10 |
No lecture: Final study time
|
|
|
|
8/11 |
No lecture: Final study time
|
|
|
|
8/12 |
Final
|
|
|
|