1A Engineering design denotes the process of fashioning a product made for a practical goal in the presence of constraints. 1B Counter that increments from 0 to 15. Latch Flip-flop 1C Any rules that mean "Don't cheat". 1D 75 ==> 1001011 0.875 ==> 0.111 75.875 = 1001011.111 1E 1111 11011 +10111 ------- 110010 1F MOS that has a dot = PMOS (Hint to memorize that: P has a circle) otherwise = NMOS a. PMOS b. Current flows from high voltage to low voltage A = source ; D = drain c. A and B connected 2A a. Inductor b. Capacitor c. Resistor d. Diode e. Transformer 2B E = 1/2(CV^2) = 1/2(0.01*10^(-6)*2^2) = 0.02*10^(-6) J 2C AC-to-DC Transformer Solar cell LED (light-emitting diode) Remote control 2D Sequential logical circuits employ memory/feedback, in addition to being combinatorial logical circuits. Combinatorial (com bi ar tor ri lo) logical circuits are circuits of which the output only depends on the input. Example of Sequential logical circuits: Flip-flop, latches Example of Combinatorial logical circuits: logic gates 4 Replace current source by open circuit. Replace voltage source by short circuit. R A o-www- .. B o-- a. V_+-0/R = I_1 I_1 = 0 (b/c current from + = 0) v_+ = 0V b. v- = v+ = 0V c. v_x = v- = 0V d. 0A e. I_0 f. I_2+0=I_3 I_3=I_2=I_0 g. 0-V_0=I_0*R V_0=-I_0*R so.. V_0/I_0-I_0*R/I_0=-R 5A PMOS and NMOS 5B HOW DOES PMOS & NMOS WORK (Useful to answer 5B) ========================= PMOS and NMOS have 3 ends. A symbol of a PMOS is shown below: +- SOURCE GATE -o|| +- DRAIN A symbol of a NMOS is shown below: +- SOURCE GATE -|| +- DRAIN **NOTE: THe following rules are not true but can solve a lot of CMOS problems if you assume that they are. A rule for PMOS: When the voltage at GATE is low, voltage at SOURCE is equal to voltage at DRAIN. A rule for NMOS: When the voltage at GATE is high, voltage at SOURCE is equal to voltage at DRAIN. (What is REAL: If the voltage of GATE respect to SOURCE is negative enough for a PMOS, There will be some voltage drop from DRAIN to SOURCE. Else, PMOS behaves like a open circuit and does not allow any current to flow through. If the voltage of GATE respect to SOURCE is positive enough for a NMOS, There will be some voltage gain from DRAIN to SOURCE. Else, NMOS behaves like a open circuit and does not allow any current to flow through.) A B C X Out 0 0 0 1 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 1 5C OR gate 6A Out = (~A)B(~C)+AB(~C)+ABC = (~A)B(~C)+AB(~C+C) = (~A)B(~C)+AB 6B A---+--+ | AND--------+ B-+----+ | | | OR-Out | +--NOT-+ | +--------AND----+ C-NOT------+ 7A micron = micrometer 1. True (smallest feature is 0.1mircon)(P.257) 2. True (P.257) 3. False (IC has lots of complicated component) 4. False (Large number of tech. companies) 7B The movement of charges produces a current. When a charge moves to the right to fill a hole, a hole is created on the charge's left. When the position of the hole is also moving, that implies some charge has been continuously filling holes. The charge has to move to fill holes. When the charge moves, a current is produced. 7C One of the two solutions I can think of: material = p-type if it has excess holes Gate MM II Source P NNNNNN P Drain CCCCCC Acceptor atom at X Acceptors accept electrons and create holes. 7D MEMS: Micro-electro-mechanical systems Optical projectors (operated by reflected light from small mirror) SmartDust (Sensor nodes) Electrostatic micromotor Inkjet print-head Airbag accelerometer