University of California at Berkeley
College of Engineering
Department of Electrical Engineeering and Computer Sciences
R.T. Howe EECS105 Fall 1997
Problem Set 7
Due: Wednesday, Oct 15th
Problem 1: Power Delay Product
One figure of merit for a digital technology is the power-delay
product, 
. In this problem, you will compare how 
scales as a fabrication process is scaled.
a) Consider a conservative CMOS process with
and 
. All other parameters are
given in on p.319 of the "Howe and
Sodini: Microelectronics - An Integrated Approach" book. Plot
vs. 
for spanning from 2-5V at a clock frequency of
150MHz for a minimum area CMOS inverter having 
with a fanout consisting of 2 inverters identical to initial inverter
gate. Consider that a wiring capacitance is 
of 
. You
should include 
in your estimate of 
. PMOS
should be adjusted so that 
.
b) An improved process is introduced with 
and
, 
. Repeat part a) for the new
technology.
c) For 
, how much higher can the clock frequency be
increased for the new technology over the conservative one and have
the same ?
Problem 2: NOR Gate Resizing
Consider the circuit in Figure 5.32. in the texbook.
a) Size the PMOS device so that using the worst
case.
b) Using the EECS105 process design rules from Lecture, sketch the
layout of your NOR gate.
c) Find the voltage transfer curve of this NOR gate using SPICE for
the following three cases:
(i) A only sweeps; B is low
(ii) B only sweeps; A is low
(iii) A and B sweep together
Use the standard LEVEL 1 SPICE models from Chapter 4 for the MOSFETs
(see p.244 in EECS105 textbook).