;====================================;
; TMS320C5x DSK Template             ;
; C.1996 Dept. of EECS, UC Berkeley  ;
; BY Tze-Yau William Ng Huang        ;
;------------------------------------;
; user can use data from 0980h to 2c00h
	.ds     0f00h
; Assume MCLK is set to 10 MHz
; Want switch-capacitor-frequency (SCF) to be 288 kHz
; SCF = MCLK/(2 x Counter A) 
TA      .word   18      ; SCF = 278 KHz
RA      .word   18      ; SCF = 278 KHz
; Want sampling frequency (Fs) to be 16 kHz
; Fs = SCF/(Counter B)
TB      .word   35      ; Fs = 7.9 kHz
RB      .word   35      ; Fs = 7.9 kHz
;---------------------------------------------------;
; Bit definition of the control register in the AIC ;
;---------------------------------------------------;
; | LP xx G1 G0 | SY AX LB BP|            G1  G0  gain
; |      GAIN    |  |  |  +-- BP Filter    0   0    1
; |      Synch --+  |  +----- Loopback     1   1    1
; |      Auxin -----+                      0   1    2
; +  (sinx)/x filter                       1   0    4
AIC_CTR .word   9h
;--------------------------------------------------------;
; AICINIT: This routine initializes the 'C50 serial port ;
;          and the TLC320C40's (AIC) TA,RA,TB,RB and     ;
;          control registers                             ;
;--------------------------------------------------------;
	 .mmregs
	 .ps     980h
AICINIT: SPLK    #20h,TCR           ; To generate 10 MHz from Tout
	 SPLK    #01h,PRD           ; for AIC master clock
	 MAR     *,AR0
	 LACC    #0008h             ; Non continuous mode
	 SACL    SPC                ; FSX as input
	 LACC    #00c8h             ; 16 bit words
	 SACL    SPC
	 LACC    #080h            ; Pulse AIC reset by setting it low
	 SACH    DXR
	 SACL    GREG
	 LAR     AR0,#0FFFFh
	 RPT     #10000           ; and taking it high after 10000 cycles
	 LACC    *,0,AR0          ; (.5ms at 50ns)
	 SACH    GREG
	 ;------------------------
	 LDP     #TA              ;
	 SETC    SXM              ;
	 LACC    TA,9             ; Initialize TA and RA register
	 ADD     RA,2             ;
	 CALL    AIC_2ND          ;
	 ;------------------------
	 LDP     #TB
	 LACC    TB,9             ; Initialize TB and RB register
	 ADD     RB,2             ;
	 ADD     #02h             ;
	 CALL    AIC_2ND          ;
	 ;------------------------
	 LDP     #AIC_CTR
	 LACC    AIC_CTR,2        ; Initialize control register
	 ADD     #03h             ;
	 CALL    AIC_2ND          ;
	 RET                      ;
;
AIC_2ND: LDP     #0               ; Data page point is 0  (MM regs)
	 SACH    DXR              ; send ACChi 00
	 CLRC    INTM             ; enable interrupts
	 IDLE                     ; wait for interrupt
	 ADD     #6h,15           ; 0000 0000 0000 0011 XXXX XXXX XXXX XXXX b
	 SACH    DXR              ; send ACChi to initiate secondary protocol
	 IDLE                     ; wait for interrupt
	 SACL    DXR              ; send the T register data
	 IDLE                     ; wait for interrupt
	 LACL    #0               ; clear ACClo
	 SACL    DXR              ; send another to make sure 1st word got sent
	 IDLE                     ; wait for interrupt
	 SETC    INTM
	 RET                      ;
;-----------------------;
; Set up the ISR vector ;
;-----------------------;
	 .ps     080ah         ;
rint:    B       RECEIVE       ;0A; Serial port receive interrupt RINT.
xint:    B       TRANSMIT      ;0C; Serial port transmit interrupt XINT.
;--------------------------;
; TMS32C05X INITIALIZATION ;
;--------------------------;
	 .ps     0a00h
	 .entry
	 SETC    INTM             ; Disable interrupts
	 LDP     #0               ; Set data page pointer
	 OPL     #0834h,PMST      ; OR the status register
	 LACC    #0
	 SAMM    CWSR             ; Set software wait state to 0
	 SAMM    PDWSR            ;
; Reset AIC by writing to PA2 (address >52) to DSK
	 SPLK    #022h,IMR        ; Using XINT syn TX & RX
	 CALL    AICINIT          ; initialize AIC and enable interrupts
;
	 CLRC    OVM              ; OVM = 0 normal accumulator overflow
	 SPM     0                ; PM = 0  no shift when transferring to ALU
;-----------------------------;
; end of the template section ;
;=============================;