EE241: Advanced Digital Integrated Circuits

Project Final Reports

Logic and Arithmetic

  • Viability of Bipolar logic for CPU's - Peter Mardahl, Ramaprabhu Srinivasan - peterm/sram@eecs

  • Low Supply Voltage Comparison of XOR/Selector Gate and SOI CMOS CPL Adder Logic -- Sang Won Son and Greg Gruber (sangwon@cory.eecs, gruber@violet)

  • Manchester Chain Implementation Using Ultra Low Voltage SOI Technology -- Xiang Lu, Zhongshi Du (xlu@alethes.eecs, zsdu@hammerhead.eecs )

  • Algorithmic Power and Area Considerations in Iterative Multipliers - Ian O'Donnell and Dennis Yee - {ian,dyee}@eecs

  • Self-Timed PLA's -- William Chang and Lloyd Huang

  • Adiabatic approach to digital computation - Alberto Ferrari (aferrari@ic.berkeley.edu). Project

    Interconnect

  • Modeling of Interconnect Delay at the Logic Level (Postscript) -- Amit Narayan (narayan@ic.eecs.berkeley.edu)

  • Interconnect Crosstalk in Digital Circuits -- Richard Schenker and Charles Fields (schenker/cfields)@eecs

  • Low Swing Interconnect -- Tony Lin , James Chen, - tlin@queme.eecs, jamesc@eecs

  • A Bootstrapped CMOS Buffer for Low Voltage Applications - Wai Lau and Li Lin - lw@eecs, linli@eecs

    Timing

  • Data-driven Communication Networks for Array Processors - Hui (Thomas) Zhang , David Pini (hui@eecs, dpini@eecs)

    Memories

  • Prospects for Floating Body SOI DRAM -- D. Park and D. Sinitsky (dgpark/sinitsky@eecs)

  • Subthreshold-Current Reduction Technique for Low-Voltage Giga-Scale Memory & Logic - Bin Yu & Zuoqin Wang , - byu@bsim.eecs, zuoqin@swordfish.eecs

  • IRAM - Integrating Processors and DRAM on a Single Chip - Bruce McGaughy & Jone Chen - brucemcg@eecs, jfchen@eecs

  • Considerations in Memory Design for IRAM -- James Young

  • Multi-logic level DRAM -- Varghese George and Jeff Gilbert - varg@eecs, gilbertj@eecs

    Various

  • Low Power FPGAs - Jeff Weldon and Carol Barrett - weldon/cjb@eecs

  • DC/DC power converters using phase-lock loop techniques -- Bill Clark and Nick Lindert, bclark@eecs nlindert@eecs

  • Digital Oversampled Delta-Sigma Demodulator -- Edwin Chan and Monico Ortiz - edwinc@eecs, monico@eecs

  • Superconductive Two-loop Sigma-Delta Modulator Design - Yiqun Xie (yqxie@hammerhead.eecs)

  • CMOS Scaling rules for Low Power Applications in GHz range. - Raji Ramesh, raji@physics