(1) Algorithmic Power Considerations in Iterative Multipliers (Proposal) - Ian O'Donnell and Dennis Yee - {ian,dyee}@eecs For channel estimation with a DS-SS-CDMA radio, a complex division is necessary at high speeds on the hand-held receiver. It is desirable to attempt to fully integrate the radio on-chip and thus the channel estimation must be done in a minimum of die area. We intend to explore methods of multiplication/division that meet the computation requirements with minimal power and area.

(2) Viability of Bipolar logic for CPU's - Peter Mardahl, Ramaprabhu Srinivasan - peterm/sram@eecs Some companies (Exponential)claim that bipolar technology can match CMOS in size and power consumption while exceeding CMOS performance. The project is to compare a CMOS and a bipolar implementation of a "typical" logic function.

(3) DRAM cell and sence amp design using SOI - D. Park and D. Sinitsky (dgpark/sinitsky@eecs) Silicon-on-Insulator technology is considered to be a good alternative to the conventional bulk Si technology. We will use the newly developed BSIM3 SOI code to evaluate cell refresh/junction leakage issues in design as well as sence amp design in SOI DRAM.

(4) Applications of Boostrapping In 90's - Wai Lau and Li Lin - lw@eecs, linli@eecs Boostrapping techniques used to be popular in NMOS only logic design to boost the gate drive. They dissappeared when CMOS logic became popular. Nowadays, increasing demand of reducing the power consumption drives the supply voltage lower and lower. In DRAM design, the voltage can be as low as 1V. To keep the speed of the circuit at this low voltage, boostraping techniques have re-emerged. Some applications include low-voltage DRAM, and low-voltage BiCMOS buffer design. We will study these existing techniques, and try to apply them to other circuit problems such as off-chip buffer or bus driver.

(5) Interconnect Crosstalk in Digital Circuits - Richard Schenker and Charles Fields (schenker/cfields)@eecs We plan to investigate the issues and limitations of crosstalk in Digital IC's. We will first study methods of calculating interconnect capacitances and inductances between interconnects lines. Both hand and simulation techniques will be explored. Using these results for different interconnect geometries and material, we will try to use Spice to model crosstalk between interconnect lines. We will also try to apply a transmission line analysis for hand calculations and predictions of crosstalk. Our work will begin on current generation type layouts, but will more closely scrutinize likely future technologies. The effects of additional interconnect layering and well as faster clock speeds will be looked at. We will also investigate the effects of using smaller supply voltages as well as multi-level voltage lines on crosstalk in Digital applications.

(6) IRAM - Integrating Processors and DRAM on a Single Chip - Bruce McGaughy & Jone Chen - brucemcg@eecs, jfchen@eecs With production DRAM memory chips approaching 1Gbit densities in the next several years, it may become possible to integrate logic and DRAM on the same chip to effectively create a computer on a single chip. However, DRAM processes differ considerably from those used to fabricate ASICs or even SRAMs. We will investigate what the significant differences are between the processes, and attempt to estimate the performance of logic in future DRAM processes.

(7) Low-Power MOS Logic Implementation -- Sang Won Son and Greg Gruber (sangwon@cory.eecs, gruber@violet) The reduction of power consumption requires optimizations at all levels of the design procedure: algorithmic, architectural, logical, and layout. We plan to explore the reduction of power consumption via clever implementation of logic by doing a comparison study of cutting-edge multi-input gate structures and overall logic schemes.

(8) Multi-logic level DRAM -- Varghese George and Jeff Gilbert - varg@eecs, gilbertj@eecs DRAM is popular due to its high bit-density. In order to improve upon this, we are investigating the storage of multiple logic levels in a given cell. Many issues arise relating to speed, power, reliability, and density. Additionally the read-write operation may have to be implemented quite differently than in standard bi-level DRAMs.

(9) Digital Oversampled Delta-Sigma Demodulator -- Edwin Chan and Monico Ortiz - edwinc@eecs, monico@eecs The digital delta-sigma demodulator in the oversampling D/A converter is made up of standard blocks, like registers, adders and comparators. We plan to investigate ways to lower the power of the demodulator. We will first study where the most power is consumed within the system, then utilize system and/or circuit techniques to minimize the power. Also, we will investigate the issue of clock jitter in the delta sigma demodulator, which can be a problem in the analog sigma-delta modulator.

(10) Memory Performance Considerations in an IRAM processor - James Young
DRAM designs are typically optimized for operation with the traditional RAS/CAS memory interface. In an IRAM processor, the processor and memory reside together on a single die, so the DRAM does not need to deliver its data off-chip. Hence many design choices exist as to how to interface the DRAM to the processor(s). This project will explore the performance and architectural consequences of a variety of possible designs.

(11) CMOS Scaling rules for Low Power Applications in GHz range. - Raji Ramesh, raji@physics To study the design of optimum device structures in terms of non quasistatic electron transport models, leakage currents in thin oxides and dissipations due to other parasitic effects. And to explore the possibility of electronic waveguides with low dissipation as interconnects.

(12) Low Swing Interconnect -- Tony Lin , James Chen, - tlin@queme.eecs, jamesc@eecs Large portions of power consumed by microprocessors is due to the switching of large interconnect e.g. clock lines, buses, etc. This project will investigate different possibilities for low swing interconnect in order to reduce power consumption. This will be done using different power supplies to drive the interconnect and a sense amplifier to receive it at the other end. We will be looking at different sense amplifier topologies as well as different tradeoffs between the driver and the receiver.

(13)SOI on Digital Circuit Design (Proposal) -Xiang Lu, Zhongshi Du (xlu@alethes.eecs, zsdu@hammerhead.eecs ) There is a possibility that SOI will become a mainstream technology at around 0.18um level. The thin SOI technology can solve the shallow junction problem, eliminate bulk punchthrough, have less parasitic capacitance and less subthreshold swing therefore lower tolerable Vt. However, several critical issues, such as thin vs. thick SOI, fully depleted (FD) or partial depleted (PD) stucture etc., still need to be addressed. In this term project, we'll explore from circuit and device point of view the benifits and trade-offs of SOI on digital design.

(14) Self-Timed Circuits for Low Power - Hui (Thomas) Zhang , David Pini (hui@eecs, dpini@eecs) With increasing die area and operating frequencies, a global synchronizing clock is becoming a severe challenge due to problems of clock skew and increasing power consumption of clock network. As a potential solution, self-timing is possible to become a mainstream design technique. Our aim is to investigate the plethora of recent self-timing techniques and evaluate their performance in terms of power consumption, latency, and ease of implementation.

(15) Superconductive Two-loop Sigma-Delta Modulator Design - Yiqun Xie (yqxie@hammerhead.eecs) The possibility of building a superconductive two-loop delta-sigma analog-to-digital (ADC) is exploited. A quantum accuracy D/A converter with integer gain is the most challenging part and is designed here. The beauty of this digital circuit in the system is illustrated in the midterm report . The continuing work to this project will lead to the eventual target which is to use this digital circuit to build an wideband high-resolution ADC which is superior than any other existing ADC in the world.

(16) Impact of Scaling on Low-Power Memory -- Bin Yu & Zuoqin Wang, - byu@bsim.eecs, zuoqin@swordfish.eecs We will investigated the ultimate potential and limitations of technology scaling for low-power memory (DRAM) unit circuit. Several generations of technology will be studied. The project focus will be on both circuit / device design tradeoff between DRAM cell access speed, circuit power consumption, and other key performances.

(17) Self-Timed PLA's - William Chang and Lloyd Huang
We will contruct robust self-timed PLA's for actual use in a current microprocessor design, and explore ways to reduce latency and power, and in general have it outperform standard cell implementations. We will explore timing circuitry that scales with the PLA size for the sake of robustness and ease of use; speculation on when to activate precharge transistors for the sake of latency; and current sensing or charge sensing for the sake of low power. Project

(18) Low Power DC/DC Controller - Jeff Weldon and Carol Barrett - weldon/cjb@eecs Using DC/DC converters in battery operated electronic devices is key in reducing power consumption and increasing run-time. Current PWM controllers require expensive processing and consume tens of mW. We will examine the design issues of the controller circuitry and develop a low power solution in the standard CMOS process.

(19) Adiabatic approach to digital computation - Alberto Ferrari (aferrari@ic.berkeley.edu). In standard CMOS circuits the power consumption is mainly due to the charging-discharging mechanism: all the energy flowing from the power supply to the output capacitance is dissipated through the MOS devices. The adiabatic approach makes arbitrarily small the losses of the energy by causing the transfer to occur sufficiently slowly (i.e. adiabatically). Project

(20)DC/DC power converters using phase-lock loop techniques
Bill Clark and Nick Lindert
bclark@eecs nlindert@eecs
We will examine the use of phase-lock loops (PLLs) as the central component of the control logic for a DC/DC power converter. The heart of the system will be two voltage controlled oscillators (VCOs) such as ring oscillators. One VCO is supplied by the desired output voltage the other by the actual output of the power converter. Assuming matched components, the two VCOs can be phase locked only when the output of the converter equals the desired voltage. Most of the design will focus on stability of the PLL. Critical issues in stability include frequency of VCO operation, digital compensation logic if needed, and limiting loop gain. Performance can be measured in overall effeciency as well as ouput voltage characteristics such as ripple, output resistance, etc.

(21) Modeling of Interconnect Delay at the Logic Level
Amit Narayan (anarayan@ic.eecs.berkeley.edu)
Performance optimization at the logic level is a key step during automatic design of integrated circuits. Currently, all the systems which optimize for performance at the logic level consider only the gate delays. In this project I propose to study: 1) The effect of interconnect delay as the technology scales down. 2) If the interconnect delay is significant (which I expect it will be), come up with some model at the logic level which can be used in the logic synthesis phase. In phase 1, I will take a design at the logic level, perform layout and routing and find out the interconnect delay as a percentage of total delay for different technologies. In phase 2, I will try to identify the relevant logic level parameters (like number of fanouts) which have an effect on the total interconnect delay. This will be done by running regressions on large number of circuits. After identifying the statistically significant parameters at the logic level I will try to build a model which can serve as a suitable cost function during the logic synthesis phase.