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  Course Syllabus and Lecture Notes
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WEEK 1: Intro & Physical Design

Overview of the Register-Transfer Level Design Flow

  • IC Problem specifications
  • System design
  • IC description at RTL in HDL
  • HDL & Logic verification & synthesis
  • Circuit Fabrics and their Evolution
  • Computational Issues in Physical Design

Data Structures for Physical Design (pdf)

  • Role of Computational Geometry
  • Representing geometry & its characteristics
  • Representing Connectivity
  • Cell-based Design

References

Logic Synthesis, S. Devadas, A. Ghosh, K. Keutzer, McGraw-Hill, 1994 (Chapters 1 & 2)

T. Szymanski and C. Van Wyk, "Layout Analysis and Verification," in Physical Design Automation of VLSI Sytems,Benjamin/Cummings, 1988, B. Preas and M. Lorenzetti, editors

G. Kedem, "The Quad-CIF Tree: A Data Structure for Hierarchical On-Line Algorithms", Proc. 19th Design Automation Conference, pp.352-357, June 1982

H. S. Baird, " Fast Algorithms for LSI Artwork Analysis," Journal of Design Automation and Fault Tolerant Computing, Vol. 2, pp.179-209, 1978

Week 2: Timing Analysis & Timing Optimization

Models for physical design (pdf)

  • RC Modeling
  • Elmore Time Constant
  • Penfield-Rubinstein approach
  • AWE
  • Statistical characteristics of wiring
  • Device Delay Modeling
  • Gate Delay modeling

Static timing analysis and verification (pdf)

  • Topological analysis
  • False path analysis
  • Transistor-level timing optimization
  • Transistor Sizing
  • TILOS approach
  • Lagrangian Multiplier Approaches
  • Convex programming approach

References

J. K. Ousterhout, "A Switch-Level Timing Verifier for Digital MOS VLSI," IEEE Trans. CAD, vol.. 4, pp. 336-349, 1985.

J. Rubinstein, P. Penfield, and M. Horowitz, "Signal Delay in RC Tree Networks," IEEE Trans. CAD, vol 2, no. 3, pp.202-211, 1983.

L. T. Pillage and R. A.  Rohrer. "Aymptotic waveform evaluation for timing analysis," IEEE Trans. on CAD, vol. 9, no. 4, pp.352-366, April 1990.

W. E. Donath, "Placement and Average lnterconnection Lengths of Computer Logic," IEEE Transactions on Circuits and Systems, April 1979

W R. Heller, W. F. Mikhail and W. E. Donath, "Prediction of Wiring Space Requirements for LSI,"  Journal of Design Automation and Fault Tolerant Computing, May 1978

Logic Synthesis. S. Devadas, A. Ghosh, K. Keutzer, McGraw-Hill, 1994 (Chapter 8.1 – 8.4)

WEEK 3: Routing & Symbolic Layout

Routing (pdf)

  • Global routing
  • Detailed routing
  • Problem definition: layers, vias, etc.
  • Generalized routing (Maze)
  • Channel routing
  • Switchbox
  • Cleanup & compaction

Algorithms for Compaction (pdf)

  • Constraint Representation
  • 2-D Compaction
  • 1-D Approaches

References:

M. Sarrafzadeh, C. K. Wong, "An Introduction to VLSI Physical Design," Mc Graw-Hill, 1996, pp. 91-139

J. Burns and A. R. Newton, "Efficient constraint generation for hierarchical compaction," Proc. IEEE Int. Conf. Computer Design, Rye, NY, October 1987, pp. 197-200.

J. Burns and A. R. Newton, "SPARCS: A new constraint-based IC symbolic layout spacer," Proc. IEEE 1986Custom Integrated Circuit Conference, Rochester, NY, May 12-15, 1986, pp. 534-539.

Hill, Shugard, Fishburn, Keutzer, "Algorithms and Techniques for VLSI Layout Synthesis," Kluwer Academic Press,

WEEK 4: Floorplanning, Partitioning & Placement

Floorplanning (pdf)

  • What is floorplanning?
  • Tutte's approach
  • Partitioning-based techniques (K-L, F-M)
  • Introduction to Simulated annealing

Placement (pdf)

  • General problem
  • Quality metrics & constraints
  • Analytical approaches (Quadratic Assignment)
  • Gordian

References

C. J. Alpert and A. B. Kahng, "Recent Directions in Netlist Partitioning: A Survey", Integration: The VLSI Journal 19 (1995), pp. 1-81.

M. Sarrafzadeh, C. K. Wong, "An Introduction to VLSI Physical Design," Mc Graw-Hill, 1996, pp. 47-69

WEEK 5: Introduction to Combinational Logic Optimization

Two-Level Logic (pdf)

  • Review canonical form
  • PLA format
  • Tautology
  • Disjoint-Sharp
  • Elements of Espresso
  • Putting it together

Multi-Level Logic optimization (pdf)

  • Boolean networks
  • Kernels & factoring: Algebraic vs Boolean
  • Rectangular Covering
  • Transitive Don't Cares

References

Logic Synthesis. S. Devadas, A. Ghosh, K. Keutzer, McGraw-Hill, 1994 (Chapter 3.1-4.6, 6.1-6.2, 7.1 – 7.6

WEEK 6: Technology Mapping

Technology Mapping (pdf)

  • Characterizing a library as a forest of trees
  • Dynamic programming
  • Dagon

Timing Driven Multi-level logic optimization (pdf)

  • Technology-independent optimizations
  • Technology dependent optimizations
  • Power optimization

References

Logic Synthesis. S. Devadas, A. Ghosh, K. Keutzer, McGraw-Hill, 1994 (Chapter 6.1-6.2, 7.1 – 7.6,  7.7-7.9)

Logic Synthesis. S. Devadas, A. Ghosh, K. Keutzer, McGraw-Hill, 1994 (Chapter 8.4-8.6)

WEEK 7: Review of key algorithmic concepts in CAD

Poly-time algorithms (pdf)

  • Longest/shortest path
  • Solving systems of inequalities
  • Union-find problems
  • Hashing

NP-hard problems (1,2,pdf1,pdf2)

  • Unate covering
  • Binate covering
  • Utility
  • Branch and Bound

References

Professor's Notes

WEEK 8: Sequential Circuit Design

Finite-State Machines (pdf)

  • The state assignment problem
  • Approaches to State assignment

Retiming (1,2,pdf1,pdf2)

  • What is retiming and why is it useful?
  • Arrival times, latches, flip-flops
  • Leiserson/Sax
  • Rudell/Shenoy
  • Retiming and resynthesis

References

N. Shenoy, "Retiming: Theory and practice", Integration: The VLSI Journal 21 (1997), pp. 1-21.

WEEK 9: Verification

Introduction to Logic simulation

  • Compiled approaches
  • Event-driven simulation
  • Hybrid approaches & caching
  • Special-purpose hardware

Binary Decision Diagrams (pdf)

  • Introduction to BDDs
  • Canonical form and ROBDDs
  • Efficient data structures for manipulating BDDs
  • The BDD package
  • Equivalence checking

References

Logic Synthesis. S. Devadas, A. Ghosh, K. Keutzer, McGraw-Hill, 1994 (Chapter 6.3-6.4)

Week 10: The Register Transfer Level

Introduction to RTL descriptions (pdf)

  • What is an RTL model?
  • Expressing RTL models in Hardware Description Languages

Formal models of computation (pdf)

  • Putting it Together
  • Integrating the entire implementation flow

References

Logic Synthesis. S. Devadas, A. Ghosh, K. Keutzer, McGraw-Hill, 1994 (Chapter 2)

WEEK 11: Manufacturing Test

Introduction to Test and Combinational ATPG (pdf)

  • What is the test problem?
  • Identification versus diagnosis
  • controlability/observability
  • Role of don't cares in test
  • Combinational test generation

Sequential Testing and Delay Testing (pdf)

  • Design-for-Test approaches
  • Scan/LSSD
  • Delay-fault testing

References

Logic Synthesis. S. Devadas, A. Ghosh, K. Keutzer, McGraw-Hill, 1994 (Chapter 9)

WEEK 12: System on a Chip

Microprocessors and their software environments (pdf)

  • Embedded microprocessor descriptions

Regular structures: datapath, PLA, etc. (pdf)

  • Introduction to Layout Styles
  • Memories and other macro blocks

References:

WEEK 13: Advanced Algorithmic Concepts

Computational complexity and CAD

  • Complexity of logic optimization
  • Computational complexity of physical design problems

Advanced algorithmic approaches

  • Probabilistic Branch and Bound
  • Other approaches
  • Advanced Probabilistic Techniques (Bayes, SVM)

References

K. Keutzer, D. Richards, "Computational Complexity of Logic Optimization’’.

S. James Press, "Bayesian statistics: principles, models, and applications", New York: Wiley, c1989

Vladimir N. Vapnik, "The nature of statistical learning theory", Springer, 1995

Week 14: Course Review

Week 15: Project Reviews

All material on this site is Copyright © Kurt Keutzer and Richard Newton, unless otherwise stated