|
Instructors Office Hours |
Dr.
Osama Khan, oukhan@eecs, Swarm Lab 490 Cory Hall Kristofer
S.J. Pister, pister@eecs.berkeley.edu,
512 Cory Hall whenever
my door is open (which is often) |
|
TA Office
Hours |
David
Burnett, sometimes |
|
Required
Texts |
none |
|
Useful
Texts |
none |
|
Grading |
show up, turn stuff in |
|
Homework |
Collaboration
is encouraged; copying is not. |
|
Lectures |
hopefully
mostly run by students |
Schedule
Week 1
Course objectives
IoT/IoE/Industry 4.0/Industrial IoT/SWARM/Cyber-Physical systems etc.
Wireless connectivity standards overview
SoC system specifications
SoC block diagram overview
CAD tools introduction
Teams formation
Technology characterization (IV curves, ft, gm/Id, Av, ro, device leakage)
Analog inverter simulation setup
Digital inverter simulation setup
Mixed signal inverter simulation setup
Comparison with commercial state-of-the-art SoC specifications
???????????
Lecture 2 (no digital notes)
Receiver architectures (Zero IF, Low-IF, super heterodyne)
Transmitter architectures (IQ up-conversion, direct modulation)
Digital system architecture
RISC-V introduction
Digital synthesis flow setup for inverter DRC+LVC clean
RISC-V verilog simulation
Ideal Matlab simulation for Tx architecture with no noise.
Ideal Matlab simulation for Rx architecture with no noise.
Week 2
SoC block diagram overview
IEEE 802.15.4/BLE PHY specifications
IEEE 802.15.4/BLE modulation
Spectral efficiency
Theoretical minimum energy per bit for the AWGN channel
Introduction to matched filter
Tx performance metrics
EVM
Spectral mask
Spurious emissions
Tx power/energy efficiency
Peak output power
Peak/average current
Rx performance metrics
??????????? Energy efficiency
??????????? Waterfall (BER) curves
??????????? Peak/average current
Matlab AWGN noise generation
Matlab Matched filter implementation
Matlab simulation for expected Tx system performance with noise
Matlab simulation for expected Rx system performance with noise
Lecture 4 (through p.18)
SoC block diagram overview
Timing violations (Setup/Hold time)
Setting Synopsis Design Compiler
Design constraints
Technology timing libraries (.lib/.db files)
Synthesis script overview
Ideal clock net specification
Gate-level Netlist verification
??????????? Timing violations
??????????? Area/power constraints
??????????? Assign statement pitfalls
Formality verification for gate-level Netlist (TBD)
Digital system performance metrics
??????????? Peak/average current
??????????? Leakage current
??????????? Area
??????????? Timing
HW
RISC-V verilog simulation with memory IP.
Digital synthesis for RISC-V with memory IP
RISC-V verilog simulation with memory IP post synthesis.
Week 3
Lecture 5 (Osama) Lecture 5
(Brad Wheeler)
SoC block diagram overview (Track Progress)
Power Management
HW
Schematic design only:
??????????? 10nA, 1uA, 10uA current reference
??????????? Analog comparator
BG voltage reference
LDO
POR reset circuitry
Temperature sensor
SoC block diagram overview (Track Progress)
Setting Synopsis IC Compiler
Design constraints
Technology timing libraries (.lib/.db files)
Synthesis script overview
Floor-planning
IO placement
Routing channels
Clock tree synthesis
Power-routing
??????????? Filler-cells
??????????????????????? Decap-cells
??????????? Integrating memory physical views
Physical Netlist verification
??????????? Timing violations
??????????? Area/power constraints
Primetime verification for physical Netlist (TBD)
HW
Place and Route RISC-V with memory IP.
RISC-V verilog simulation with memory IP post Place and Route.
Week 4
Lecture 7 (Design planning)
RISC-V architecture deep dive with
Prof. Bora or Prof. Krste
HW
Lecture 8 (David on scanchains and Fil Maksimovic on power amplifiers and LC oscillators)
SoC block diagram overview (Track Progress)
Energy harvesting power source
Frequency generation
Receiver symbol timing recovery
HW
Schematic design only:
RC oscillator
DC-DC converter
Analog symbol timing recovery loop (TBD)
Week 5
SoC block diagram overview (Track Progress)
??????????? Writing C software for RISC-V
??????????? Implementing RISC-V debug Interface
HW
Verilog simulation for RISC-V debug interface
Simple C program verification:
??????????? Verilog
??????????? Synthesized netlist
??????????? Place and Route netlist
Lecture 10
??????????? LC LO + DAC + mixer co-design by Fil
??????????? PA design by Fil
HW
Schematic design only:
??????????? LC LO + DAC
??????????????????????????????????? Image reject mixer
??????????????????????????????????? LC LO + PA??
Week 6
SoC block diagram overview (Track Progress)
Adding peripherals to the digital system
HW
RF controller verilog:
Preamble detection
SFD detection
Packet handler
CRC
FIFO buffers
Lecture 12
PGA baseband amplifier by Brad
??????????? BPF filter design by Brad
Analog amplifier for biomedical signals (TBD)
HW
Schematic design only:
??????????? PGA
??????????? BPF
??????????????????????? Analog amplifier for biomedical signals (TBD)
Week 7
Lecture 13 Guest speaker Henry Cook, SiFive Inc.
TSMC 28 nm Process Technology (28 nm PDK and IPs available on EECS servers by this time)
HW
28 nm technology characterization
Port analog schematics to 28 nm process.
Port digital system to 28 nm process.
Lecture 14
HW
Port analog schematics to 28 nm process.
Port digital system to 28 nm process.
Week 8
Lecture 15
TSMC 28 nm layout rules by someone from BWRC?
HW
Analog inverter layout in 28 nm.
PEX for the analog layout.
Post PEX simulation
Port analog schematics to 28 nm process.
Port digital system to 28 nm process.
Lecture 16 (Osama's slides) (guest ADC & layout lecture by Jaeduk
Han)
SoC block diagram overview (Track Progress)
HW
Verify analog schematic design in 28 nm process.
Verify digital system in 28 nm process.
Week 9
Lecture 17
SoC block diagram overview (Track Progress)
HW
Transmitter schematic simulation
Receiver schematic simulation
Port digital system to 28 nm process.
Lecture 18
SoC block diagram overview (Track Progress)
HW
Transmitter schematic simulation
Receiver schematic simulation
Port digital system to 28 nm process.
Week 10
Lecture 19
SoC block diagram overview (Track Progress)
??????????? Digital Timers
HW
??????????????????????? Add Timer peripheral to the digital system
Lecture 20
SoC block diagram overview (Track Progress)
Flash/SAR ADC by David
HW
??????????????????????? Flash/SAR ADC schematic design
??????????????????????? DNL/INL simulation
??????????????????????? ENOB estimation
Week 11
Lecture 20
SoC block diagram overview (Track Progress)
???????????
HW
??????????????????????? Analog layout of individual blocks
??????????????????????? PEX verification
Lecture 21
SoC block diagram overview (Track Progress)
??????????? Digital Bootloader
HW
??????????????????????? Digital test benches for verification
??????????????????????? Bootloader verification on FPGA (TBD)
Week 12
SoC block diagram overview (Track Progress)
???????????
HW
??????????????????????? Top analog simulation along with power management.
Analog layout of individual blocks
??????????????????????? PEX verification
Lecture 23
SoC block diagram overview (Track Progress)
??????????? Digital Scan-chain
HW
??????????? ??????????? Setup script for digital scan-chain
??????????????????????? Digital scan-chain verilog simulation
??????????????????????? Digital scan-chain verification post synthesis & post Place and Route
Week 13
SoC block diagram overview (Track Progress)
???????????
HW
??????????????????????? Top analog simulation with power management.
Analog layout of individual blocks
??????????????????????? PEX verification
Lecture 25
SoC block diagram overview (Track Progress)
??????????? SoC testing methodology
HW
??????????????????????? Design digital test structures
Week 14
SoC block diagram overview (Track Progress)
???????????
HW
??????????????????????? Top level Analog PEX simulation
??????????????????????? Top level Analog DRC+LVS clean
??????????????????????? Top digital DRC+LVS clean
SoC block diagram overview (Track Progress)
HW
??????????????????????? Top level Analog PEX simulation
??????????????????????? Top level Analog DRC+LVS clean
??????????????????????? Top digital DRC+LVS clean
???????????
Week 15
SoC block diagram overview (Track Progress)
???????????
HW
??????????????????????? Top SoC DRC+LVS clean
Lecture 28
SoC block diagram overview (Track Progress)
HW
??????????????????????? GDS stream out! Hell is over?
|
Week |
Date/ Notes |
Topic |
Reading
/ Resources (see links below) |
Homework |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|