Electrical Engineering 40, Fall '05
Introduction to Microelectronic Circuits
Professor Andy Neureuther, EECS

EXAMS                  EE40 Fall 2005 - Announcements & Course Info

Letter Grades Office Hours Fri 11-12 for exams and score details.
The letter grades are a bit more liberal than the raw scores. Review and comparison of finals also resulted in a few raw scores changing. Grade Scale for Final is below.

A+ 200
A 185
A- 169
B+ 154
B 139
B- 124
C+ 109
C 94
C- 69
D+ 54

Double check details of Labs and HW Total.

Final Solution:

Exams are taking longer to grade than anticipated. Thanks for the emails about exam solutions.
View exams as graded 11-12 AM and 3-4:45 PM Wed at 509 Cory.
Data entry, processing and grade decisions not likely complete till Thurs 9AM.

Material simplified from Rabaey text
{This is just in case you did not follow the switched resistor model for CMOS and the operation of the double CMOS latch for a clock signal and its complement that were covered carefully in lecture you can look at the following materials. Be careful not to be confused by the material on comparing logic types and clock overlaps that we did not cover.}
CMOS (EE 40 is not concerned with comparing logic types)
CMOS Latches (EE 40 is not concerned with clock overlap)

(Tenative) Office Hours During Finals:
        Dec 12th,   (None at the moment)
Tuesday         Dec 13th,   1-2 297 Cory Phil
Wednesday    Dec 14th,   1-2 297 Cory Isaac, 2-3:30 50 Andy
Thursday        Dec 15th,   11:45-1:15 509 Cory Andy
Friday             Dec 16th,   11-12:30 509 Cory Andy
Saturday         Dec 17th,   10-12 509 Cory Andy, 1-3 297 Isaac
Sunday           Dec 18th,    1-3 297 Phil
Homework and Lab Grades will be outside 509 Cory when ready.
Homework and Lab Materials will be outside 509 Cory when ready.
Extra Problems are available at
They are password protected (ask Bart).

COOL PROJECT EXAMPLE of a Home Run on solving differential equations for a spring and mass contributed by Neil Warren and James Johnston.

HOT NEWS: SIMPL is ALIVE again thanks to Rach Liu! Simulation of Profiles from Layout (SIMPL) allows you to view mask layouts and specify a process flow to see what they produce. Try this Open-GL beta version at http://cuervo.eecs.berkeley.edu/Volcano/simpl_gl/main.htm

EE40 News Group is at ucb.class.ee40. It is accessable by both email (pine, outlook) and web at https://inst.eecs.berkeley.edu/webnews/.  For instructions see http://inst.eecs.berkeley.edu/connecting.html#news
You need and EECS domain account. To obtain one see http://inst.eecs.berkeley.edu/connecting.html#accounts

Read and be ready to quote the EECS Academic Dishonesty Policy
Matrix of Disc and Labs

Any problems with the website? Email neureuth@eecs