Introduction to Digital Design and Integrated Circuits

Lectures, Labs, Office Hours

Lectures	Mon, Wed	11:00 am - 12:30 pm	Cory 540AB, Overflow room: Cory 293, Online	Borivoje Nikolic
Discussion	Mon	3:00 pm - 4:00 pm	Social Sciences Building 170	Alisha, Daniel, Zhaokai
	Tu	8:00 am - 9:00 am	Online	Alisha, Daniel, Zhaokai
	Wed	3:00 pm - 4:00 pm	GPB 107	Alisha, Daniel, Zhaokai
ASIC Lab	Mon	5:00 pm - 8:00 pm	Cory 111/117	Nayiri Krzysztofowicz
	Wed	8:00 am - 11:00 am	Cory 111/117, Online	Daniel Grubb
	Fri	11:00 am - 2:00 pm	Cory 111/117	Zhaokai Liu
FPGA Labs	Tue	3:00 pm - 6:00 pm	Cory 111/117	Zhenghan Lin
	Wed	6:00 pm - 9:00 pm	Cory 111/117	Vighnesh Iyer
	Thursday	11:00 am - 2:00 pm	Cory 111/117	Alisha Menon
	Fri	8:00 am - 11:00 am	Cory 111/117	Charles Hong
Office Hours	Mon	1:00 pm - 2:00 pm	Cory Courtyard	Borivoje Nikolic
	Mon	2:00 pm - 3:00 pm	Cory 111/117	Alisha Menon
	Tue	3:00 pm - 4:00 pm	Remote/Online	Daniel Grubb
	Tue	6:00 pm - 7:00 pm	Cory 111/117	Zhenghan Lin
	Wed	10:00 am - 11:00 am	Cory 111/117	Vighnesh Iyer
	Wed	2:00 pm - 3:00 pm	Cory 111/117	Charles Hong
	Th	3:30 pm - 4:30 pm	Cory 111/117, Online	Nayiri Krzysztofowicz
	Fri	2:00 pm - 3:00 pm	Cory 111/117	Zhaokai Liu

Homework

• Ask questions on our Piazza forum.
• Homeworks will be posted as links in the outline below. Please submit completed homework via Gradescope. See Piazza for the entry code.
• Homework will be released on Thursdays before midnight, and will be due next Friday 8 days later. Homework will be challenging and graded for correctness.

Exams

• Past Midterms and Finals

Course Outline

Week	Date	Lecture Topic	Recording	Optional reading	Discussion	ASIC Lab	FPGA Lab	Homework	Homework Solution
1	8/25	Class Organization & Introduction to Course Content slides (2-up) (8-up)			No Discussion	No Lab	No Lab	No homework!
2	8/30	Design Process slides (2-up) (8-up)	Lecture 2 Robustness Performance Power Cost	H&H,   Ch1,	Discussion 1 slides Discussion 1 annotated slides	Lab 1: Getting Around the Compute Environment	Lab 1: Getting Set Up	Homework 1
	9/1	Verilog I slides (2-up) (8-up)	Lecture 3		Discussion 2 slides	Lab 2: Verilog and Simulation	Lab 2: Introduction to FPGA Development
3	9/8	Verilog II slides (2-up) (8-up)		H&H,   Ch4				Homework 2	Homework 2 solution
4	9/13	Verilog III slides (2-up) (8-up)		H&H  , Ch2 or P&H, App. A	Discussion 3 slides Discussion 3 annotated slides	Lab 3: Logic Synthesis	Lab 3: More Sequential Circuits, Audio "DAC"
	9/15	Combinational Logic slides (2-up) (8-up)	Zoom recording		Discussion 4 slides Discussion 4 annotated slides			Homework 3	Homework 3 solution
5	9/20	Finite State Machines slides (2-up) (8-up)	Zoom recording	H&H, Ch. 3.4		Lab 4: Floorplanning, Placement, Power, and CTS	Lab 4: Tunable Wave Generator, NCO, FSMs, RAMs
	9/22	RISC-V ISA slides (2-up) (8-up)	Zoom recording	H&H, Ch. 6,7  or P&H, Ch. 2,4 CS61C videos (below)
6	9/27	RISC-V pipelining slides (2-up) (8-up)	Zoom recording	H&H, Ch. 7  or P&H, Ch. 4 CS61C videos (below)	Discussion 5 slides (annotated)	Lab 5: Routing	Lab 5: UART	Homework 4
	9/29	Pipelining, FPGAs slides (2-up) (8-up)	Zoom recording
7	10/4	FPGAs, CMOS slides (2-up) (8-up)	Zoom recording		Discussion 6 slides Discussion 6 annotated slides	No Lab	No Lab
	10/6	CMOS slides (2-up) (8-up)	Kaltura					Homework 5	Homework 5 Solution
	10/7	Midterm 1 Solution
8	10/11	CMOS Logic slides (2-up) (8-up)	Zoom recording	RCN, Ch. 5.1-5.4, 6.1-6.2	Discussion 7 slides Discussion 7 annotated slides	Lab 6: SRAM Integration, DRC, LVS	Lab 6: FIFO and UART Piano	Homework 6	Homework 6 solution
	10/13	CMOS Logic slides (2-up) (8-up)	Kaltura
9	10/18	Logical effort slides (2-up) (8-up)	Kaltura	RCN, Ch. 6.2	Discussion 8 slides(annotated)	ASIC Project	FPGA Project
	10/20	Wires, energy slides (2-up) (8-up)		RCN, Ch. 4				Homework 7	Homework 7 Solution
10	10/25	Adders slides (2-up) (8-up)	Kaltura	RCN, Ch. 11.1-11.3  H&H 5.2	Discussion 9 slides (annotated) (recording)			Homework 8	Homework 8 Solution
	10/27	Adders II slides (2-up) (8-up)	Kaltura		Discussion10 (p. 1-3) and midterm review (p. 4-7) slides, Discussion10 annotated, Discussion10 recording				Worksheet solutions
11	11/1	Multipliers slides (2-up) (8-up)	Kaltura
	11/3	Guest lecture, Dividers slides (2-up) (8-up)	Kaltura					Homework 9	solution
	11/4	Midterm 2 Solution
12	11/8	Latches slides (2-up) (8-up)	Zoom recording	RCN 7.1-7.2 H&H 3.1-3.3	Discussion 11 Slides (annotated)
	11/10	Latches, Flip-Flops slides (2-up) (8-up)	Kaltura
13	11/15	SRAM slides (2-up) (8-up)	Kaltura	RCN Ch. 12 H&H 5.5	Discussion 12 slides (annotated) (recording)			Homework 10	Homework 10
	11/17	Guest lecture, Decoders, Cache slides (2-up) (8-up)	Kaltura	CS61C videos below
14	11/22	Memories slides (2-up) (8-up)
15	11/29	Flash, Parallelism slides (2-up) (8-up)			Discussion 13 slides (annotated)(recording)			Homework 11	Homework 11 Solution
	12/1	Summary slides (2-up) (8-up)
	12/13	Final Exam Solution

Resources

Textbooks

• Recommended Digital Design and Computer Architecture, RISC-V ed, David Money Harris & Sarah L. Harris (H & H)
• Recommended Digital Integrated Circuits: A Design Perspective, 2nd ed, Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolić (RCN)
• Useful Computer Organization and Design RISC-V Edition, David Patterson and John Hennessy (P&H)
• Useful CMOS VLSI Design, Neil Weste, David Harris (W&H)

Verilog

• Verilog Primer Slides
• wire vs reg, from the CS150 Spring 2009 class.
• always@ blocks, from the CS150 Fall 2009 class.
• FSMs in Verilog
• Ready-Valid Interfaces

Protocols & Standards

• IEEE Verilog
• I2C Bus
• RS-232

CS61C videos

• RISC-V Assembly 1 2 3 4 5 6 7 8 9 10 11 12 13 14
• RISC-V (RV32I) Instruction Formats 1 2 3 4 5 6 7 8 9
• CPU Design 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
• Pipeline 1 2 3 4 5 6 7 8 9 10 11
• Caches 1.1 1.2 1.3 1.4 2.1 2.2 2.3 3.1 3.2 3.3 4.1 4.2 4.3 4.4

Staff

	Borivoje Nikolic	bora at berkeley dot edu
	Alisha Menon	allymenon at berkeley dot edu
	Bob Zhou	bob.linchuan at berkeley dot edu
	Charles Hong	charleshong at berkeley dot edu
	Daniel Grubb	dpgrubb at berkeley dot edu
	Nayiri Krzysztofowicz	nayiri at berkeley dot edu
	Vighnesh Iyer	vighnesh.iyer at berkeley dot edu
	Zhaokai Liu	zhaokai_liu at berkeley dot edu
	Zhenghan Lin	zhenghan_lin at berkeley dot edu

Grading

Class

Problem Sets	20%
Midterm Exam 1	20%
Midterm Exam 2	20%
Final Exam	40%

ASIC Labs

Lab Reports	37.5%
Project	62.5%

FPGA Labs

Lab Checkoffs	25%
Project	75%

Cheating Policy

• If you turn in someone else’s work as if it were your own, you are guilty of cheating.  This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
• Also, if you knowingly aid in cheating, you are guilty.
• We have software that compares your submitted work to others.
• However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
• Do not post your work on public repositories like github (private o.k.)
• If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat!  If it is a midterm exam, final exam, or final project, you get an F in the class.  All cases of cheating reported to the office of student conduct.