Introduction to Digital Design and Integrated Circuits
Course Outline
| Week | Date | Lecture Topic | Discussion | ASIC Lab | FPGA Lab | Homework | Extra resources |
|---|---|---|---|---|---|---|---|
| 1 | 08/24 | Introduction (slides) (recording) | |||||
| 2 | 08/29 | Design Process (slides) (recording) | Discussion 1 (annotated) (slides) (recording) | Lab 1 | Lab 1 | Homework 1 (solution) | H&H, Ch. 1 |
| 08/31 | Design Metrics (slides) (recording) | ||||||
| 3 | 09/05 | HDLs (slides) (recording) | Discussion 2 (annotated) (slides) (recording) | Lab 2 | Lab 2 | Homework 2 (solution) | H&H, Ch. 4 |
| 09/07 | Behavioral Verilog (slides) (recording) | H&H, Ch. 2 P&H, App. A |
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| 4 | 09/12 | Sequential Verilog, Verification (slides) (recording) | Discussion 3 (annotated) (slides) (recording) | Lab 3 | Lab 3 | Homework 3 (solution) | |
| 09/14 | Finite State Machines (slides) (recording) | H&H, Ch. 3.4 | |||||
| 5 | 09/19 | Combinational Logic, RISC-V (slides) (recording) | Discussion 4 (annotated) (slides) (recording) | Lab 4 | Lab 4 | Homework 4 (solution) | H&H, Ch. 6.7 P&H, Ch. 2, 4 CS61C videos |
| 09/21 | Combinational Logic, RISC-V (slides) (recording) | H&H, Ch. 7 P&H, Ch. 4 CS61C videos |
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| 6 | 09/26 | Pipelining (slides) (recording) | Discussion 5 (annotated) (slides) (recording) | Lab 5 | Lab 5 | Homework 5 (solution) | |
| 09/28 | FPGAs, SystemVerilog Assertions (slides) (recording) (guest lecture) | ||||||
| 7 | 10/03 | CMOS (slides) (recording) | Discussion 6 (annotated) (slides) (recording) | Lab 6 | Lab 6 | Homework 6 (solution) | |
| 10/05 | CMOS (slides) (recording) | ||||||
| 10/05 | Midterm (pdf) (solution) | ||||||
| 8 | 10/10 | CMOS Delay (slides) (recording) | Discussion 7 (annotated) (slides) (recording) | ASIC Project | FPGA Project | Homework 7 (solution) | RCN, Ch. 5.1-5.4, 6.1-6.2 |
| 10/12 | Logical Effort (slides) (recording) | ||||||
| 9 | 10/17 | Wires and Energy (slides) (recording) | Discussion 8 (annotated) (slides) (recording) | Homework 8 (solution) | RCN, Ch. 6.2 | ||
| 10/19 | Energy, Adders (slides) (recording) | RCN, Ch. 4 | |||||
| 10 | 10/24 | Adders (slides) (recording) | Discussion 9 (annotated) (slides) (recording) | Homework 9 (solution) | RCN, Ch. 11.1-11.3 H&H, Ch. 5.2 |
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| 10/26 | Multipliers (slides) (recording) | ||||||
| 11 | 10/31 | Shifters, Dividers, Timing (slides) (recording) | Discussion 10 (annotated) (slides) (recording) | Homework 10 (solution) | |||
| 11/02 | Midterm 2 (pdf) (solution) | ||||||
| 12 | 11/07 | Latches, Flip-Flops (slides) (recording) | Discussion 11 (annotated) (slides) (recording) | Homework 11 | |||
| 11/09 | SRAM (slides) (recording) | RCN, Ch. 7.1-7.2 H&H, Ch. 3.1-3.3 |
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| 13 | 11/14 | Decoders (slides) (recording) | Discussion 12 (annotated) (slides) (recording) | Homework 12 | |||
| 11/16 | Guest lecture | RCN, Ch. 12 H&H, Ch. 5.5 |
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| 14 | 11/21 | Memory (slides) (recording) | Discussion 13 (annotated) (slides) | CS61C videos | |||
| 11/23 | No Lecture (Thanksgiving) | ||||||
| 15 | 11/28 | Parallelism, Low-Power Design (slides) (recording) | Discussion 14 (annotated) (slides) (recording) | ||||
| 11/30 | Finale (slides) (recording) | ||||||
| 12/12 | Final Exam (pdf) (solution) |
Lectures, Labs, Office Hours
Homework
- Ask questions on our Ed Discussion forum.
- Homeworks will be posted as links in the outline above. Please submit completed homework via Gradescope. See Ed Discussion for the entry code.
- Homework will be released on Thursdays before midnight, and will be due next Friday 8 days later. Homework will be challenging and graded for correctness.
Exams
Resources
Textbooks
- Recommended Digital Design and Computer Architecture, RISC-V ed, David Money Harris & Sarah L. Harris (H & H)
- Recommended Digital Integrated Circuits: A Design Perspective, 2nd ed, Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolić (RCN)
- Useful Computer Organization and Design RISC-V Edition, David Patterson and John Hennessy (P&H)
- Useful CMOS VLSI Design, Neil Weste, David Harris (W&H)
Verilog
- Verilog Primer Slides
- wire vs reg, from the CS150 Spring 2009 class.
- always@ blocks, from the CS150 Fall 2009 class.
- FSMs in Verilog
- Ready-Valid Interfaces
Protocols & Standards
CS61C videos
Staff
 |
Borivoje Nikolic | bora AT berkeley DOT edu |
 |
Ken Ho (he/him) | ken_ho AT berkeley DOT edu |
 |
Hyeong Seok Oh (he/him) | hyeongseok_oh AT berkeley DOT edu |
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Rahul Kumar (he/him) | rahulkumar AT berkeley DOT edu |
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Viansa (Ansa) Schmulbach | ansa AT berkeley DOT edu |
 |
Lux Zhang (he/him) | iansseijelly AT berkeley DOT edu |
 |
Lucy Meng (she/her) | lucymeng AT berkeley DOT edu |
 |
Nikhil Jha | nikhiljha AT berkeley DOT edu |
 |
Oliver Yu (he/him) | oliveryu AT berkeley DOT edu |
 |
Rohan Kumar (he/him) | rohankumar AT berkeley DOT edu |
 |
Edison Wang | ruofeng_01 AT berkeley DOT edu |
 |
Thomas Matthew (he/him) | twmatthew AT berkeley DOT edu |
 |
William Li (he/him) | williamlyh AT berkeley DOT edu |
Grading
Class
| Homeworks | 20% |
| Midterm 1% | 20% |
| Midterm 2% | 20% |
| Final Exam | 40% |
ASIC Labs
| Lab Reports | 37.5% |
| Project | 62.5% |
FPGA Labs
| Lab Checkoffs | 25% |
| Project | 75% |
Honor Code
- If you turn in someone else’s work as if it were your own, you are guilty of cheating. This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
- Also, if you knowingly aid in cheating, you are guilty.
- We have software that compares your submitted work to others.
- However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
- Do not post your work on public repositories like github (private o.k.)
- If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat! If it is a midterm exam, final exam, or final project, you get an F in the class. All cases of cheating reported to the office of student conduct.