| 1 |
1/22 |
Class Organization & Introduction to Course Content slides |
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Lab 1 (Getting Around the Compute Environment) |
Lab 1 (Setup Accounts, Verilog Intro, FPGA Basics) |
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1/24 |
Design Alternatives & ASIC Flow slides |
Discus. 1 |
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HW1 Solution |
| 2 |
1/29 |
Verilog Part 1 slides |
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Lab 2 (Verilog Simulation) |
Lab 2 (FPGA Toolchain, FPGA Mapping, Tone Gen) |
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1/31 |
Verilog Part 1 continued |
Discus. 2 |
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HW2 Solution |
| 3 |
2/5 |
Verilog Part 2 - Sequential Elements slides |
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Lab 3 (Logic Synthesis) |
Lab 3 (Simulation, ROM-based music playback) |
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2/7 |
FPGA Architecture slides |
Discus. 3 |
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HW3 Solution |
| 4 |
2/12 |
Boolean Algebra slides |
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Lab 4 (Floorplanning, Placement and Power Routing) |
Lab 4 (Synchronization, Debouncer, Resets, FSM) |
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2/14 |
Finite State Machines slides |
Discus. 4 |
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HW4 Solution |
| 5 |
2/19 |
CMOS Devices and Processing slides |
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Lab 5 (CTS and Routing) |
Lab 5 (Serial I/O, building UART transmitter) |
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2/21 |
CMOS Circuits (CL, State Elements, Wires) slides |
Discus. 5 |
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HW5 Solution |
| 6 |
2/26 |
Circuit Timing, part 1 slides |
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Lab 6 (Power and Timing Verification) |
Lab 6 (FIFOs, UART Piano) |
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2/28 |
Circuit Timing, part 2 slides |
Discus. 6 |
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HW6 Solution |
| 7 |
3/5 |
Power and Energy slides |
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Lab 7 (SRAM Integration) |
Preliminary Project Specification Release |
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3/7 |
RISC-V Processor Implementation slides |
Discus. 7 Handout |
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| 8 |
3/12 |
Midterm 1 Review Exam Topics, slides |
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Project Released (Timeline overview) |
Project Released (Subject to Change) |
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3/14 |
Midterm 6-9PM (in Soda 306 - HP Auditorium) - no class |
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| 9 |
3/19 |
Accelerators slides |
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Project Checkpoint 1 |
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3/21 |
Memory Circuits slides |
Discus. 8 Handout |
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| 10 |
3/26 |
No classes (Spring Recess) |
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Project Checkpoint 1 |
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HW7 Solution |
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3/28 |
No classes (Spring Recess) |
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| 11 |
4/2 |
Power/clock distribution slides |
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4/4 |
Memory Blocks slides |
Discus. 9 Handout |
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HW8 Solution |
| 12 |
4/9 |
Parallalism and Design Optimization slides |
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Project Checkpoint 2 |
Project Checkpoint 2 |
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4/11 |
Adders slides |
Discus. 10 |
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HW9 Solution |
| 13 |
4/16 |
Multipliers slides |
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Project Checkpoint 3 |
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| |
4/18 |
High Level Synthesis and Deep Neural Nets slides |
Discus. 11 |
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| 14 |
4/23 |
More Multipliers, Counters, LFSRs, Shifters slides |
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| |
4/25 |
List Processor Example slides |
Discus. 12 |
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HW10 Solution |
| 15 |
4/30 |
Faults in ICs slides |
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Project Checkpoint 4 |
Project Checkpoint 3, Interview |
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5/2 |
Wrap-up and Exam Review Exam Topics,slides |
Discus. 13 Handout |
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| RRR Week |
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No classes |
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Project Interview |
Final Project Checkoff Logistics |
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| Exam Week |
5/17 |
Final Exam 7–10PM (in Hearst Gym 251) |
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Project Report Due |
Project Report Due |
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