1 |
1/21 |
Class Organization & Introduction to Course Content slides webcast |
Discussion 1 (Intro) |
Lab 1 (Getting Around the Compute Environment) |
Lab 1 (Getting Set Up) |
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1/23 |
Design Alternatives & ASIC Flow slides webcast |
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HW 1 Solutions |
2 |
1/28 |
Verilog Part 1 slides webcast |
Discussion 2 (Verilog Simulation) |
Lab 2 (Simulation) |
Lab 2 (Introduction to FPGA Development) |
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1/30 |
Verilog Part 2 slides webcast |
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HW 2 Solutions |
3 |
2/4 |
FPGA Architecture slides webcast |
Discussion 3 (LUTs, Boolean Algebra) |
Lab 3 (Logic Synthesis) |
Lab 3 (Simulation, Button Parser) |
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2/6 |
Combinational Logic, Boolean Algebra slides webcast |
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HW 3 Solutions |
4 |
2/11 |
Finite State Machines 1 slides webcast |
Discussion 4 (Finite State Machines) |
Lab 4 (Floorplanning, Placement, and Power) |
Lab 4 (FPGA Memory Blocks, I2S Audio) |
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2/13 |
Finite State Machines 2 slides webcast |
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HW 4 Solutions |
5 |
2/18 |
CMOS slides webcast |
Discussion 5 (CMOS) |
Lab 5 (Parallelization and Routing) |
Lab 5 (Ready/Valid FIFO, HDMI Display) |
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2/20 |
CMOS Part 2 slides webcast |
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HW 5 (Updated) Solutions |
6 |
2/25 |
Circuit Timing slides webcast |
Discussion 6 (CMOS Timing SPICE Simulations) |
Lab 6 (SRAM Integration with Vector Dot Product) |
No new lab this week |
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2/27 |
Circuit Timing Part 2 slides webcast |
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HW 6 (Updated) Solutions |
7 |
3/3 |
RISC-V Microarchitecture and Implementation slides webcast |
Discussion 7 (Timing, Zoom OH) |
No new lab this week |
Lab 6 (UART, Drawing Triangle) |
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3/5 |
RISC-V Part 2 (catch up) slides webcast |
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HW 7 Solutions |
8 |
3/10 |
Exam 1 Review slides webcast |
Discussion 8 (RISC-V, Zoom OH) |
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3/12 |
No Class - Exam 6-9PM |
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Project Specification (Chkpt 1, 2, 3, 4) |
Project Specification (Chkpt 1, 2, 3, 4) |
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9 |
3/17 |
Power and Energy slides webcast |
Discussion 9 (Power and Memory) |
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3/19 |
Memory Blocks slides webcast |
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Checkpoint 1 due |
Checkpoint 1 due |
HW 8 Solutions |
10 |
3/24 |
Spring Recess |
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3/26 |
Spring Recess |
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11 |
3/31 |
Memory Blocks part 2, (start) Parallelism and Design Optimization slides webcast |
Discussion 10 (Caches and Parallelism/Pipelining) Zoom Recording |
Checkpoint 3 Released (Cache) |
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4/2 |
Parallelism, (start) List Processor Example slides webcast |
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Checkpoint 1.1 due |
HW 9 Solutions |
12 |
4/7 |
List Processor Example, (start) Adders webcast |
Discussion 11 (RTL, List Processor, Scheduling) Zoom Recording |
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4/9 |
Deep Neural Networks Design Examples slides webcast |
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Checkpoint 2 due |
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HW 10 Solutions |
13 |
4/14 |
Adders slides webcast |
Discussion 12 (Adders, Multipliers) Zoom Recording |
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Checkpoint 2 due |
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4/16 |
Multipliers, Counters, Shifters slides webcast |
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HW 11 Solutions |
14 |
4/21 |
Clock and Power Distribution slides webcast |
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Checkpoint 3 Released (conv2D) |
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4/23 |
Faults, Error Correction Codes slides webcast |
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Checkpoint 3 due |
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HW 12 Solutions |
15 |
4/28 |
Wrap-up and Exam Review slides webcast |
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Checkpoint 4 Released (tape-in!) |
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4/30 |
Exam 2 7-10 PM |
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Checkpoint 3 due |
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16 |
5/5 |
RRR No Lecture |
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Checkpoint 4 Released (100MHz/Sobel) |
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5/7 |
RRR No Lecture |
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Checkpoint 4 due + Interview |
Checkpoint 4 due + Demo |
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