Letures, Labs, Office Hours

Lectures Tue, Thu 3:30 pm - 5:00 pm 540AB Cory John Wawrzynek
Discussion Fri 9:00 am - 10:00 am 540AB Cory Quincy Huynh
ASIC Lab Wed 5:00 pm - 8:00 pm 125 Cory Tan Nguyen
FPGA Labs Wed 2:00 pm - 5:00 pm 125 Cory Tan Nguyen
  Thu 11:00 am - 2:00 pm 125 Cory Tan Nguyen
Office Hours Thu 2:30 pm and by appointment 631 Soda John Wawrzynek
  Wed 1:00 pm - 2:00 pm 125 Cory Tan Nguyen
  Thu 2:00 pm - 3:30 pm 125 Cory Tan Nguyen
  Fri 10:00 am - 11:00 am 540AB Cory Quincy Huynh

Discussions, Homework

  • Ask questions on our Piazza forum.
  • Homeworks will be posted as links in the outline below and announced on Piazza. Please submit completed homework via Gradescope. See Piazza for the entry code.

Course Outline

Week Date Lecture Topic Discussion ASIC Lab FPGA Lab Homework
1 1/21 Class Organization & Introduction to Course Content slides webcast Discussion 1 (Intro) Lab 1 (Getting Around the Compute Environment) Lab 1 (Getting Set Up)  
  1/23 Design Alternatives & ASIC Flow slides webcast       HW 1 Solutions
2 1/28 Verilog Part 1 slides webcast Discussion 2 (Verilog Simulation) Lab 2 (Simulation) Lab 2 (Introduction to FPGA Development)  
  1/30 Verilog Part 2 slides webcast       HW 2 Solutions
3 2/4 FPGA Architecture slides webcast Discussion 3 (LUTs, Boolean Algebra) Lab 3 (Logic Synthesis) Lab 3 (Simulation, Button Parser)  
  2/6 Combinational Logic, Boolean Algebra slides webcast       HW 3 Solutions
4 2/11 Finite State Machines 1 slides webcast Discussion 4 (Finite State Machines) Lab 4 (Floorplanning, Placement, and Power) Lab 4 (FPGA Memory Blocks, I2S Audio)  
  2/13 Finite State Machines 2 slides webcast       HW 4 Solutions
5 2/18 CMOS slides webcast Discussion 5 (CMOS) Lab 5 (Parallelization and Routing) Lab 5 (Ready/Valid FIFO, HDMI Display)  
  2/20 CMOS Part 2 slides webcast       HW 5 (Updated) Solutions
6 2/25 Circuit Timing slides webcast Discussion 6 (CMOS Timing SPICE Simulations) Lab 6 (SRAM Integration with Vector Dot Product) No new lab this week  
  2/27 Circuit Timing Part 2 slides webcast       HW 6 (Updated) Solutions
7 3/3 RISC-V Microarchitecture and Implementation slides webcast Discussion 7 (Timing, Zoom OH) No new lab this week Lab 6 (UART, Drawing Triangle)  
  3/5 RISC-V Part 2 (catch up) slides webcast       HW 7 Solutions
8 3/10 Exam 1 Review slides webcast Discussion 8 (RISC-V, Zoom OH)      
  3/12 No Class - Exam 6-9PM   Project Specification (Chkpt 1, 2, 3, 4) Project Specification (Chkpt 1, 2, 3, 4)  
9 3/17 Power and Energy slides webcast Discussion 9 (Power and Memory)      
  3/19 Memory Blocks slides webcast   Checkpoint 1 due Checkpoint 1 due HW 8 Solutions
10 3/24 Spring Recess        
  3/26 Spring Recess        
11 3/31 Memory Blocks part 2, (start) Parallelism and Design Optimization slides webcast Discussion 10 (Caches and Parallelism/Pipelining) Zoom Recording Checkpoint 3 Released (Cache)    
  4/2 Parallelism, (start) List Processor Example slides webcast     Checkpoint 1.1 due HW 9 Solutions
12 4/7 List Processor Example, (start) Adders webcast Discussion 11 (RTL, List Processor, Scheduling) Zoom Recording      
  4/9 Deep Neural Networks Design Examples slides webcast   Checkpoint 2 due   HW 10 Solutions
13 4/14 Adders slides webcast Discussion 12 (Adders, Multipliers) Zoom Recording   Checkpoint 2 due  
  4/16 Multipliers, Counters, Shifters slides webcast       HW 11 Solutions
14 4/21 Clock and Power Distribution slides webcast     Checkpoint 3 Released (conv2D)  
  4/23 Faults, Error Correction Codes slides webcast   Checkpoint 3 due   HW 12 Solutions
15 4/28 Wrap-up and Exam Review slides webcast   Checkpoint 4 Released (tape-in!)    
  4/30 Exam 2 7-10 PM     Checkpoint 3 due  
16 5/5 RRR No Lecture     Checkpoint 4 Released (100MHz/Sobel)  
  5/7 RRR No Lecture   Checkpoint 4 due + Interview Checkpoint 4 due + Demo  

Staff

john photo John Wawrzynek johnw at berkeley dot edu
tan photo Tan Nguyen tan.nqd at berkeley dot edu
quincy photo Quincy Huynh quincy.huynh at berkeley dot edu

Resources

Homework Policy

Homework will be released on Fridays before midnight, and will be due on the Monday 10 days later. Homework will be challenging and graded for correctness.

Grading

Class

Problem Sets 30%
Midterm Exam 1 30%
Midterm Exam 2 40%

ASIC Labs

Lab Reports 37.5%
Project 62.5%

FPGA Labs

Lab Checkoffs + Reports 25%
Project 75%

Cheating Policy

  • If you turn in someone else’s work as if it were your own, you are guilty of cheating.  This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
  • Also, if you knowingly aid in cheating, you are guilty.
  • We have software that compares your submitted work to others.
  • However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
  • Do not post your work on public repositories like github (private o.k.)
  • If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat!  
If it is a midterm exam, final exam, or final project, you get an F in the class.  All cases of cheating reported to the office of student conduct.