| 1 |
1/19 |
Class Organization & Introduction to Course Content (slides) (video) |
Discussion 1 (slides)(video) |
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1/21 |
Design Alternatives & ASIC Flow (slides)(video) |
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Homework 1 (Solutions) |
| 2 |
1/26 |
Verilog Part 1 (slides)(video) |
Discussion 2 (slides)(video) |
Lab 1 (Getting Around the Compute Environment) |
Lab 1 (Getting Setup, FPGA Board, Vivado, Basic Verilog) |
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1/28 |
Verilog Part 2 (slides)(video) |
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Homework 2 (Solutions)(Verilog Definitions) |
| 3 |
2/2 |
FPGA Architecture (slides)(video) |
Discussion 3 (slides)(video) |
Lab 2 (Simulation) |
Lab 2 (Sequential Circuits, Vivado Simulation, Button Parser) |
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2/4 |
Combinational Logic, Boolean Algebra (slides)(video) |
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Homework 3 Solutions |
| 4 |
2/9 |
Finite State Machines 1 (slides)(video) |
Discussion 4 (slides)(video) |
Lab 3 (Logic Synthesis) |
Lab 3 (FPGA Memory Blocks) |
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2/11 |
Finite State Machines 2 (slides)(video) |
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Homework 4 Solutions |
| 5 |
2/16 |
CMOS Circuits 1 (slides)(video) |
Discussion 5 (slides)(video) |
Lab 4 (Floorplanning, Placement, and Power) |
Lab 4 (Handshake) |
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2/18 |
CMOS Circuits 2 (slides)(video) |
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Homework 5 Solutions |
| 6 |
2/23 |
Circuit Timing Part 1 (slides)(video) |
Discussion 6 (slides)(video) |
Lab 5 (Parallelization and Routing) |
Lab 5 (UART) |
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2/25 |
Circuit Timing Part 2 (slides)(video) |
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Homework 6 Solutions |
| 7 |
3/2 |
RISC-V Microarchitecture and Implementation (slides)(video) |
Discussion 7 (slides)(video) |
Lab 6 (SRAM Integration with Vector Dot Product) |
Project Specification (Chkpt 1, 2, 3, 4) |
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3/4 |
RISC-V Part 2 (slides)(video) |
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| 8 |
3/9 |
Exam 1 Review (slides)(exam1-information.pdf) |
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3/11 |
No Class - Exam 6-9PM (Exam Policy)(Exam Questions)(Exam Solutions) |
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| 9 |
3/16 |
Power and Energy (slides)(video) |
Discussion 8 (slides)(video) |
Project Specification (Chkpt 1) |
Checkpoint 1 due |
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3/18 |
Memory Blocks 1 (slides)(video) |
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Homework 7 Solution |
| 10 |
3/23 |
Spring Recess |
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3/25 |
Spring Recess |
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| 11 |
3/30 |
Memory Blocks part 2 (slides)(video), (start) Parallelism and Design Optimization |
Discussion 9 (slides)(video) |
Checkpoint 1 due (4/2 @ 4PM PDT), Checkpoint 2 released |
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Homework 8 Solution |
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4/1 |
Parallelism (slides)(video), (start) List Processor Example |
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| 12 |
4/6 |
List Processor Example (slides)(video), (start) Adders |
Discussion 10 (video) |
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Homework 9 Solution |
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4/8 |
Deep Neural Networks Design Examples (slides(video)) |
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| 13 |
4/13 |
Adders (slides)(video) |
Discussion 11 (slides)(video) |
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Checkpoint 2 due |
Homework 10 Solution |
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4/15 |
Multipliers, Shifters (slides)(video) |
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Checkpoint 3, 4 Released (CNN, 100MHz) |
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| 14 |
4/20 |
Clock and Power Distribution (slides)(video) |
Discussion 12 (slides)(video) |
Checkpoint 2 due, , Checkpoint 3 & 4 Released |
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Homework 11 Solution |
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4/22 |
Testing, Faults, Error Correction Codes (slides)(video) |
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| 15 |
4/27 |
Inside Logic Synthesis Tools (slides)(video) |
Discussion 13 (slides)(video) |
Checkpoint 3 due |
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4/29 |
Wrap-up and Exam Review (slides)(video)(exam information) |
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| 16 |
5/5 |
RRR No Lecture |
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Checkpoint 4 |
Final Checkoff due |
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5/7 |
RRR No Lecture |
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| FINAL |
5/14 |
No Class - Final Exam 7-10 PM (Final Exam Policy)(Final Exam Questions) |
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