Course Outline

  • Ask questions on our Ed forum for this semester.
  • Homeworks will be posted as links in the outline below.
  • Please submit completed homework via Gradescope.

Lecture Playlist

Lab/OH Queue Form

Week Date Lecture Topic Discussion ASIC Lab FPGA Lab Homework
1 1/17 Class Organization & Introduction to Course Content (slides)(recording) Discussion 1 (slides) Lab 0   Homework 1 (solution)
  1/19 Design Alternatives (slides)(recording)        
2 1/24 Verilog Part 1 (slides) Discussion 2 (slides) Lab 1 Lab 1 Homework 2 (solution)
  1/26 Verilog Part 2 (slides)        
3 1/31 FPGA Architecture (slides) Discussion 3 (slides) Lab 2 Lab 2 Homework 3 (solution)
  2/2 Combinational Logic, Boolean Algebra (slides)        
4 2/7 Finite State Machines 1 (slides) Discussion 4 (slides) Lab 3 Lab 3 Homework 4 (solution)
  2/9 Finite State Machines 2 (slides)        
5 2/14 CMOS Devices and Circuits 1 (slides) Discussion 5 (slides) (recording)   Lab 4 Homework 5 (solution)
  2/16 CMOS Circuits 2 (slides)        
6 2/21 Circuit Timing Part 1 (slides) Discussion 6 (slides) (recording) Lab 4   Homework 6 (solution)
  2/23 Circuit Timing Part 2 (slides)        
7 2/28 RISC-V Microarchitecture and Implementation (slides) Discussion 7 (slides) (recording)   Lab 5  
  3/2 Midterm Review (slides)        
8 3/7 RISC-V Part 2 (slides)   Lab 5    
  3/9 No Class - Midterm 6-9PM (exam) (solution)        
9 3/14 Finish RISC-V and Project Discussion 8 (slides) (recording) Project Spec + Ckpt 1 Project Spec Homework 7 (solution)
  3/16 Memory Blocks 1 (slides)        
10 3/21 Guest Lecture: Formal Verification and Logic Synthesis (slides), ML for CAD (slides)   Ckpt 2    
  3/23 Memory Blocks 2 (slides)        
11 3/28 Spring Recess        
  3/30 Spring Recess        
12 4/4 Parallelism (slides) Discussion 9 (slides) (recording)   Project Grading Policy Homework 8 (solution)
  4/6 List Processor Example Design (slides)        
13 4/11 Power and Energy (slides) Discussion 10 (slides) (recording) Ckpt 3   Homework 9 (solution)
  4/13 Catchup        
14 4/18 Adders (slides) Discussion 11 (slides) (recording) Ckpt 3 (1 wk), Ckpt 4 (2 wks)   Homework 10 (solution)
  4/20 Multipliers, Shifters (slides)        
15 4/25 Clock and Power Distribution (slides) Discussion 12 (slides) (recording)   Project Report Guidelines Homework 11 (solution)
  4/27 Wrap-up and Exam Review (slides)        
16 5/2 RRR No Lecture        
  5/4 RRR No Lecture   Final Checkoff (Report due midnight 5/8)    
FINAL 5/10 No Class - Final Exam 11:30A - 2:30P, Physics Building 4        

Lectures, Labs, Office Hours

Content Days Times Location Staff
Lectures Tu, Th 9:30 am - 11:00 am Soda 306 John Wawrzynek
Discussion Fri 2:00 pm - 3:00 pm Cory 540AB Rahul Kumar
  Fri 3:00 pm - 4:00 pm Cory 540AB Yukio Miyasaka
ASIC Lab Tu 11:00 am - 2:00 pm Cory 111/117 Lux Zhang
FPGA Labs Mon 8:00 am - 11:00 am Cory 111/117 Rahul Kumar
  Mon 11:00 am - 2:00 pm Cory 111/117 Yukio Miyasaka
  Mon 2:00 pm - 5:00 pm Cory 111/117 Yukio Miyasaka
  Mon 5:00 pm - 8:00 pm Cory 111/117 Dhruv Vaish
Office Hours Th 3:00 pm - 4:00 pm Cory 111/117 Lux Zhang
  W 4:00 pm - 6:00 pm Cory 111/117 Dhruv Vaish
  Th 12:30 pm - 1:30 pm Soda 631 John Wawrzynek
  Fri 1:00 pm - 2:00 pm Cory 111/117 Rahul Kumar
  Fri 4:00 pm - 5:00 pm Cory 111/117 Yukio Miyasaka

Discussions, Homework

  • Conceptual and homework questions should be directed to Ed forum for this semester.
  • Homeworks will be posted as links in the outline, available in PDF format.
  • Please submit completed homework via Gradescope. Homework will be released on Fridays before midnight, and will be due on the Monday 10 days later.

Staff

john photo John Wawrzynek johnw at berkeley dot edu
yukio photo Yukio Miyasaka yukio_miyasaka at berkeley dot edu
rahul photo Rahul Kumar rahulkumar at berkeley dot edu
lux photo Lux Zhang iansseijelly at berkeley dot edu
dhruv photo Dhruv Vaish dvaish at berkeley dot edu
daniel photo Daniel Endraws daniel.endraws at berkeley dot edu

Resources

Previous Exams

Homework Policy

Homework will be released on Fridays before midnight, and will be due on the Monday 10 days later. Homework will be challenging and graded for correctness.

Grading

Class

Problem Sets 30%
Participation 5%
Midterm 30%
Final 35%

ASIC Labs

Lab Reports 25%
Project 75%

FPGA Labs

Lab Checkoffs + Reports 25%
Project 75%

Cheating Policy

  • If you turn in someone else’s work as if it were your own, you are guilty of cheating.  This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
  • Also, if you knowingly aid in cheating, you are guilty.
  • We have software that compares your submitted work to others.
  • However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
  • Do not post your work on public repositories like github (private o.k.)
  • If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat! 
If it is a midterm exam, final exam, or final project, you get an F in the class.  All cases of cheating reported to the office of student conduct.