Lectures and Office Hours

Lectures Tues, Thurs 9:30 am - 11:00 am Cory 540AB Borivoje Nikolic, Sophia Shao, Vladimir Stojanovic
Discussion Fri 10:00 am - 11:00 am Cory 540AB Erik Anderson
Office Hours Thurs 11:00 am - 12:00 pm Virtual Borivoje Nikolic
Tues 2:00 pm - 3:00 pm Virtual Sophia Shao
TBD Vladimir Stojanovic
Thurs 3:00 pm - 4:00 pm Virtual Erik Anderson



  • There will be four quizzes during the semester.
  • Final exam will be held during the last week of the course.

Course Outline

Class Date Lecture Topic Recording Reading Lab Discussion Homework Homework Solution
1 1/18 Intro (1-up) (2-up) (8-up) Zoom Moore03
2 1/20 Chipyard (1-up)
Zoom Alon20 Lab 1 (due 1/28)
3 1/25 Design Productivity slides Zoom Chisel Bootcamp
4 1/27 SystemVerilog (1-up) (2-up) (8-up) Zoom Lab 2 (due 2/4) Zoom
5 2/1 System Interconnect I slides Zoom
6 2/3 System Interconnect II slides Zoom Lab 3 (due 2/11) Zoom
7 2/8 Accelerator Integration slides Zoom
8 2/10 Scaling
(1-up) (2-up) (8-up)
Zoom Lab 4 (due 2/25) Zoom
9 2/15 Technology features
(1-up) (2-up) (8-up)
10 2/17 Transistor models
(1-up) (2-up) (8-up)
Zoom Sodini84
Toh88 Sakurai90
11 2/24 Standard Cells (1-up) (2-up) (8-up) Zoom Lab 5 (due 3/11) Zoom Hw 1 (due 3/4) Hw 1 Solutions
12 3/1 Standard Cells 2 (1-up) (2-up) (8-up) Zoom
13 3/3 Timing (1-up) (2-up) (8-up) Zoom Partovi01 Zoom
14 3/8 Latches (1-up) (2-up) (8-up) Zoom Partovi01
15 3/10 Variability
(1-up) (2-up) (8-up)
Zoom Bernstein06 Zoom
16 3/12 Veriability cont. and Memory slides Zoom
17 3/17 SRAM Guest Lecture
18 3/29 SRAM Peripherals(1-up)
Amrutur98 Niki11 Osada04 Hw 2 (due 4/4) Hw 2 Solutions
19 3/31 Power-Performance Tradeoff slides Zoom
20 4/5 Lowering supplies (1-up) (2-up) (8-up) Zyuban04 Chandrakasan95 Rabaey Ch.4 Hw 3 (due 4/13) Hw 3 Solutions
21 4/7 DVFS (1-up) Zoom Burd00
22 4/12 Leakage and Sleep Modes(1-up) Zoom
23 4/14 Optimal Thresholds, Supplies (1up)
(2-up) (8-up)
Hw 4 (due 4/22) Hw 4 Solutions
24 4/19 Clock Generation (1-up)
25 4/21 Supply Generation (1-up)
Zoom Wong06
26 4/26 Finale Zoom
27 4/28 Final Exam
28 5/3
29 5/5



  • Optional Low Power Design Essentials, J. Rabaey, Springer, 2009.
  • Baseline Digital Integrated Circuits: A Design Perspective, Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolić
  • Useful CMOS VLSI Design, Neil Weste, David Harris
  • Useful Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE Press, 2001.


bora photo Borivoje Nikolic bora at berkeley dot edu
sophia photo Sophia Shao ysshao at berkeley dot edu
vlada photo Vladimir Stojanovic vlada at berkeley dot edu
erik photo Erik Anderson erik dot f dot anderson at berkeley dot edu



Assignments 20%
Design Project 40%
Quizzes 10%
Final Exam 30%

Cheating Policy

  • If you turn in someone else’s work as if it were your own, you are guilty of cheating.  This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
  • Also, if you knowingly aid in cheating, you are guilty.
  • We have software that compares your submitted work to others.
  • However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
  • Do not post your work on public repositories like github (private o.k.)
  • If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat!  
If it is a midterm exam, final exam, or final project, you get an F in the class.  All cases of cheating reported to the office of student conduct.