Strategic Computing and Communications Technology Group H: Standards Final Report
The battle between Verilog and VHDL has been raging in the Electronic Design Automation (EDA) Industry since the mid-'80s. The battle between these two competing software languages is a particularly interesting case because of the economic, competitive, and governmental issues that are involved. What also makes this case interesting is that the struggle between these two competing standards is currently in full-swing and is without a clear victor.
Verilog and VHDL are software languages used by electronic engineers to specify the design of integrated circuits (ICs) or electronic systems. The use of a software language to describe a complex hardware design enables engineers to modify and verify designs without the need of building costly and time-consuming prototypes. Once verified through simulation, these software representations are then transformed into an actual hardware product.
The Verilog Hardware Description Language, usually just called Verilog, was designed and first
implemented by Phil Moorby at Gateway Design Automation in 1984 and 1985. It was first used beginning in 1985 and was extended substantially through 1987.
The implementation was the Verilog simulator sold by Gateway. The first major extension was Verilog-XL, which added a few features and implemented the infamous "XL algorithm" which was a very efficient method for doing gate-level simulation. This occurred in 1986, and marked the beginning of Verilog's growth period. Many leading-edge electronic designers began using Verilog at this time because it was fast at gate level simulation, and had the capabilities to model at higher levels of abstraction. These users began to do full system simulation of their designs, where the actual logic being designed was represented by a netlist and other parts of the system were modeled behaviorally.
In 1988, Synopsys delivered the first logic synthesizer which used Verilog as an input language. This was a major event, as now the top-down design methodology could actually be used effectively. The design could be done at the "register transfer level", and then Synopsys' Design Compiler could translate that into gates. With this event, the use of Verilog increased dramatically.
Beginning in 1989, the second major trend began to emerge, and that was the use of Verilog-XL for sign-off certification by ASIC vendors. As Verilog became popular with the semiconductor vendors customers, they began to move away from their own, proprietary simulators, and started allowing customers to simulate using Verilog-XL for timing certification. As more ASIC vendors certified Verilog-XL, they requested more features, especially related to timing checks, back annotation, and delay specification. In response, Gateway implemented many new features in the language and the simulator to accommodate this need.
Cadence Design Systems acquired Gateway in December 1989, and continued to market Verilog as both a language and a simulator. At the same time, Synopsys was marketing the top-down design methodology, using Verilog. This was a powerful combination.
VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. It can describe the behavior and structure of electronic systems, but is particularly suited as a language to describe the structure and behavior of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional MSI circuits.
The development of VHDL was initiated in 1981 by the United States Department of Defense (DoD) to address the hardware life cycle crisis. The cost of reprocuring electronic hardware as technologies became obsolete was reaching crisis point, because the function of the parts was not adequately documented, and the various components making up a system were individually verified using a wide range of different and incompatible simulation languages and tools. The requirement was for a language with a wide range of descriptive capability that would work the same on any simulator and was independent of technology or design methodology.
Below is a summary of the history of VHDL:
There is a stark contrast between the standardization process of VHDL and Verilog. It is interesting to note here that although the standardization methods were quite different, the resulting products are both quite strong and experts cannot agree as to which is better.
The standardization process for VHDL was unique in that the participation and feedback from industry was sought at an early stage. A baseline language (version 7.2) was published 2 years before the standard so that tool development could begin in earnest in advance of the standard. All rights to the language definition were given away by the DoD to the IEEE in order to encourage industry acceptance and investment.
DoD Mil Std 454 mandates the supply of a comprehensive VHDL description with every ASIC delivered to the DoD. The only way to provide the required level of description is to use VHDL\ throughout the design process.
As an IEEE standard, VHDL must undergo a review process every 5 years (or sooner) to ensure its ongoing relevance to the industry. The first such revision was completed in September 1993.
All this time, Verilog was a proprietary language. No other vendors were allowed to make a Verilog simulator. In response, the other CAE vendors put their weight behind the VHDL standardization process which had been started by the DoD in the early 1980's. They needed a comparable product to sell, and VHDL was the only viable alternative.
By 1990, Cadence began to feel the pressure of selling a proprietary product (Verilog) against an open standard product (VHDL). Potential Verilog customers were very concerned about dealing with a single-source vendor for such an expensive and strategically critical product. Competing EDA vendors wanted to break Cadence's stranglehold on the software design tool market by pushing the VHDL. Cadence recognized that if Verilog remained a closed language, the pressures of standardization would eventually cause the industry to shift to VHDL. Consequently, Cadence organized Open Verilog International (OVI), and in 1991 gave it the documentation for the Verilog Hardware Description Language. This was the event which "opened" the language. Subsequently, OVI did a considerable amount of work to improve the Language Reference Manual (LRM), clarifying things and making the language specification as vendor-independent as possible.
In 1994, the IEEE 1364 working group was formed to turn the OVI LRM into an IEEE standard. This effort was concluded with a successful ballot in 1995, and Verilog became an IEEE standard in December, 1995.
When Cadence gave OVI the LRM, several companies began working on Verilog simulators. In 1992, the first of these were announced, and by 1993 there were several Verilog simulators available from companies other than Cadence. The most successful of these was VCS, the Verilog Compiled Simulator, from Chronologic Simulation. This was a true compiler as opposed to an interpreter, which is what Verilog-XL was. As a result, compile time was substantial, but simulation execution speed was much faster.
Now, Verilog simulators are available for most computers at a variety of prices, and which have a variety of performance characteristics and features. Verilog is more heavily used than ever - it has truly become a standard hardware description language.
EDA tools were once a veritable "Roach Motel" of design knowledge your intellectual property could check in, but it could never check out. Oh sure, you might coerce your favorite tool to plot a graphic here or spew out a report there, but once it took hold of your design data and saved it to some gnarled hexadecimal format, it pretty much had you in its claws. Any mention of sharing library data across multiple vendors would have evoked hysterical fits of laughter from the vendor's field support engineer. Today, no one laughs. The challenges facing designers raise the required level of integration and interaction across tools and libraries, which are necessary for multi-vendor solutions. EDA standards are now seen as a necessity to support leading-edge design flows, since these flows will increasingly require tighter coupling across a suite of concurrent tools from several vendors. The Semiconductor Industry Association (SIA) recognizes EDA technology as a critical enabler. In the SIA's 1994 "National Technology Roadmap For Semiconductors," EDA standards-related barriers are dominant throughout the Design and Test thrust roadmaps. In the white paper titled "Design Needs forthe 21st Century," sponsored by Semiconductor Research Corp. (SRC), similar conclusions are drawn. Industry-wide EDA standards are consistently identified as crucial to close the widening "design gap" between design tools and manufacturing capability. In response, Sematech is now partnering with the Electronic Design Automation Companies (EDAC) and the CAD Framework Initiative (CFI) to define a common solution for the electronics industry, known as the EDA Industry Standards Roadmap. This roadmap, when complete, will be used to guide investment priorities for the development and evolution of EDA standards into the next decade. While this isn't the first attempt at standards coordination, widespread buy-in from a diverse array of stakeholders sets this effort apart from the rest. Below is a description of other standardization issues in the Verilog and VHDL case.
Verilog and VHDL are expensive and complex products. The average selling price for a single seat of either a Verilog or VHDL software package is $150,000. Given that large electronics organizations can employ thousands of IC or systems engineers, investments in VHDL or Verilog software packages can exceed $50 million.
Verilog and VHDL have a very long learning curve, even for sophisticated engineers. A complete training course typically lasts two weeks, enabling an engineer to begin using the product. It is estimated that 6 months to 1 year of use is required to become proficient in VHDL or Verilog. The languages are sufficiently different to have little knowledge carry-over.
Given the large capital investment required and the long learning curves for these products, electronic design companies must standardize on one product or another. Once the choice is made, the company is locked-in.
Verilog began as a proprietary language developed by Gateway Design Automation in 1985. Gateway was acquired by Cadence Design Systems in 1989. Cadence strongly marketed the Verilog language and it captured a large percentage of the non-DoD IC design market.
The EDA industry grew rapidly in the mid-80s and competition was extreme. Verilog was a proprietary language, making it difficult for other EDA companies to develop complementary products around Verilog, which would enable these EDA companies to sell to the lucrative IC design customer. These other EDA companies wanted to break the Cadence stranglehold on the IC design market by putting their weight behind VHDL, which was an open language.
Cadence had invested millions of dollars on the acquisition of the Verilog language and had invested millions more in research and development to improve the language. Investors placed a large amount of intellectual property value on Cadence's Verilog language. In 1990, Cadence management decided that if Verilog remained a proprietary language, it would eventually lose out to VHDL, an open language with many competing vendors. In 1991, Cadence officially published the Verilog language and it became an open language.
The United States "Cold War" machine was in full swing in the early-'80s. Governmental contracts worth billions of dollars were being issued to defense contractors to develop and design sophisticated electronic systems to be used in stealth fighters or "Star Wars" systems. Many of these systems required the collaboration of many defense contractors, with each contractor working on a specific piece of the overall system.
The government was concerned that given the state of fragmented development tools, with each contractor using its own proprietary software design tool, design delays would be enormous during the integration phase. In an attempt to counteract these potential design delays, the government helped develop a specification for a software design tool and mandated that all products developed under a government contract must use this new software design tool. This tool is the VHDL software design language.
By issuing such a mandate, the United States government legitimized the VHDL standard. Whether the VHDL standard was a good one or not, defense contractors had to use it. The government used its purchasing power to convert a new standard into a powerful commercial entity.
The primary lesson learned from this case is that owners of proprietary technology must be very aware of the competitive landscape. Potential competition from an open standard technology can quickly lead to disaster for a company that is selling a proprietary product. Customers will avoid single-source, proprietary products if there is a supplementary product that is open and has multiple sources. Once a decision is made to open up a product such as Verilog, it should be done as quickly and professionaly as possible in order to make a clear statement. There should be no confusion about the move from a proprietary to an open standard.