NTU 6341 / EECS 141

Digital Integrated Circuits

Fall 2007 References


J. Rabaey, A. Chandrakasan, B. Nikolic,  Digital Integrated Circuits: A Design Perspective , 2nd Edition, Prentice Hall, 2003.

Other Books:

S. Narendra and A. Chandrakasan, "Leakage in Nanometer CMOS Technologies", Springer, 2006.

B. Wong et al, "Nano-CMOS Circuit and Physical Design", Wiley, 2005.

C. Piguet Ed, "Low Power Electronics Design" CRC Press, 2004.

A. Chandrakasan, W. Bowhill, F. Fox, "Design of High-Performance Microprocessor Circuits", IEEE Press, 2001.

W.J. Dally and J.W. Poulton, "Digital System Engineering", Cambridge University Press, 1998.

K. Bernstein, et al, "High Speed CMOS Design Styles", Kluwer Academic Publishers, 1998.

V.G. Oklobdzija, "High-Performance System Design: Circuits and Logic", IEEE Press, 1999.

A. Chandrakasan and R. Brodersen, "Low-Power CMOS Design", IEEE Press, 1998

Selected Papers:

Scaling Perspectives and Limits

J. Meindl, Low Power Microelectronics: Retrospect and Prospect, Proceedings of the IEEE, April 1995.

B. Davari et al., CMOS Scaling for High Performance and Low Power - The Next Ten Years, Proceedings of the IEEE, April 1995.

S. Borkar, Design challenges of technology scaling. IEEE Micro, vol.19, no.4,  p.23-29, July-Aug. 1999.

S. Chou, Innovation and Integration in the Nanoelectronics Era, Proceedings ISSCC 2005, Feb. 2005.

Delay and Timing Modeling - Performance Optimization

K.Keutzer, Delay Modeling and Static Timing Verification, Lecture Notes EE244

Stojanovic et al, Methods for True Power Optimization, ICCAD 2002. (presentation slides)

Timing and Synchronization

David Messerschmitt, Synchronization in Digital System Design, JSAC, Oct 90.


Other readings:

Journal of Solid State Circuits

International Solid-State Circuits Conference Digests of Technical Papers and Slide Supplements

Symposium on VLSI Circuits, Digests of Technical Papers 

International Symposium on Low Power Electronic Design