NTU 6342 / EECS 241

Advanced Digital Integrated Circuits

Spring 2007

ANNOUNCEMENTS:

(04/08/07) HW #3 solutions are posted in the Homework page

(03/27/07) HW #4 is posted in the Homework page (Due 4/6/07)

(03/01/07) HW #3 is posted in the Homework page (Due 3/16/07)

(02/27/07) HW #2 solutions are posted in the Homework page

(02/06/07) HW #1 solutions are posted in the Homework page

(02/01/07) HW #2 is posted in the Homework page (Due 2/16/07)

(01/15/07) HW #1 is posted in the Homework page (Due 1/25/07)

(01/15/07) Updated the Project page to include possible project areas and links to past projects.

(01/15/07) First conference call is on Tuesday (01/16/07) at 9:30 am PT.

(01/15/07) The website is up. Check here often for updates.

 

DESCRIPTION:

The aim of this course is to convey a knowledge of advanced concepts of circuit design for digital LSI and VLSI components in state-of-the-art MOS technologies.

Emphasis is on circuit design, and optimization of either very high-speed or low-power circuits for use in applications such as microprocessors, signal and multimedia processors, communications, memory and periphery.

Special attention will be devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing.

INSTRUCTOR: Jan M. Rabaey

 

COURSE CONSULTANT:

Louis P. Alarcn

Email: lalarcon at eecs dot berkeley dot edu

Office hours: Tuesdays/Thursdays 4-5 pm PT

Phone: (510) 642 5776

Fax: (510) 643 5877

 

CONTACT INFORMATION:

For course content and prerequisites, contact the course consultant. For information regarding registration, pricing or other administrative items, contact the CalVIEW office:

 

CALVIEW OFFICE

205 McLaughlin Hall

University of California, Berkeley

Berkeley, CA 94720

Phone: (510) 642-5776

Fax: (510) 643-5877

Email: ntu at coe dot berkeley dot edu

Web Page: www.coe.berkeley.edu/calview