Handouts for CS250: VLSI Systems Design
Fall 2010
Lab 1 (Version 083010a): GCD: VLSI's Hello World
- Version 083010a: initial posting
Lab 2 (Version 092010a): Write and Synthesize a Two-Stage/Three-Stage RISC-V v2 Processor
- Version 091310a: initial posting
- Version 092010a: fixed register instruction naming in the
instruction table. The format should be inst xc,xa,xb.
Lab 3 (Version 092110a): ASIC Implementation of a RISC-V v2 Core with On-Chip Caches
- Version 092010a: initial posting
- Version 092110a: major change. upgrade lab harness. register grant signals coming out from the arbiter on the negative edge.
Tutorial 1 (Version 083010a): Using SVN to Manage Source RTL
- Version 083010a: initial posting
Tutorial 2 (Version 091210a): Bits and Pieces of CS250's toolflow
- Version 083010a: initial posting
- Version 090110a: changed manuals directory
- Version 091210a: add link for HDL Compiler for Verilog User Guide
Tutorial 3 (Version 091110b): Build, Run, and Write RISC-V Programs
- Version 091110a: initial posting
- Version 091110b: minor typo fix
Tutorial 4 (Version 091210a): Simulating Verilog RTL using Synopsys VCS
- Version 091110a: initial posting
- Version 091210a: major change. need to change lab
harness. now pc+4 relative.
Tutorial 5 (Version 091210b): RTL-to-Gates Synthesis using Synopsys Design Compiler
- Version 091210a: initial posting
- Version 091210b: major change. need to change lab
harness. now pc+4 relative.
Tutorial 6: Automatic Placement and Routing using Synopsys IC Compiler
Tutorial 7: Power Analysis using Synopsys PrimeTime PX
Tutorial 8: UC Berkeley's SRAM Model Compiler
Tutorial 9: UC Berkeley's Cache Model Compiler
RISC-V Specification: RISC-V Spec