Letures, Labs, Office Hours

Lectures Mon, Wed 2:30 pm - 4:00 pm 540AB Cory Borivoje Nikolic and Sophia Shao
Discussion Fri 10:00 am - 11:00 am 521 Cory Vighnesh Iyer
Mon 1:00 pm - 2:00 pm 540AB Cory Cem Yalcin
ASIC Lab Fri 11:00 am - 2:00 pm 125 Cory Cem Yalcin
FPGA Labs Mon 8:00 am - 11:00 am 125 Cory Ryan Kaveh
Tue 8:00 am - 11:00 am 125 Cory Vighnesh Iyer
Thu 5:00 pm - 8:00 pm 125 Cory Rebekah Zhao
Office Hours Mon 11:00 am - 12:00 pm 509 Cory Borivoje Nikolic
Tue 10:00 am - 11:00 am 125 Cory Cem Yalcin
Wed 11:00 am - 12:00 pm 570 Cory Sophia Shao
Wed 4:00pm - 5:00 pm 125 Cory Vighnesh Iyer
Thu 3:00 pm - 4:00 pm 125 Cory Ryan Kaveh
Fri 2:00 pm - 3:00 pm 125 Cory Rebekah Zhao

Homework

  • Ask questions on our Piazza forum.
  • Homeworks will be posted as links in the outline below. Please submit completed homework via Gradescope. See Piazza for the entry code.
  • Homework will be released on Thursdays before midnight, and will be due next Friday 8 days later. Homework will be challenging and graded for correctness.

Exams

  • Past Midterms and Finals
  • Midterm 1: 10/2 (2:30 - 4:00 pm) (Cory 540AB: Last name A-L, Genetics & Plant Biology 103: Last name M-Z )
    • Midterm 1 Review Session: 9/30 (7:00 - 8:30 pm) (Tan Hall 180) slides
  • Midterm 2: 11/6 (2:30 - 4:00 pm) (Cory 540AB: Last name A-H, Cory 277: Last name I-Z)
    • Midterm 2 Review Session: 11/5 (7:00 - 8:30 pm) (Kroeber Hall 155) slides

Course Outline

Week Date Lecture Topic Discussion ASIC Lab FPGA Lab Homework Homework Solution
1 8/28 Class Organization & Introduction to Course Content slides webcast Discussion 1 (Intro) Lab 1 (Getting Around the Compute Environment) Lab 1 (Setup Accounts, Verilog Intro, FPGA Basics) No homework!
2 9/4 Design Process slides webcast Discussion 2 (Noise Margins, Verilog, Simulation) code Lab 2 (Simulation) Lab 2 (Introduction to FPGA Development) HW 1 HW 1 solution
3 9/9 Verilog I slides webcast Discussion 3 (Verilog Simulation, Parameterized Modules) code Lab 3 (Logic Synthesis) Lab 3 (Tone Generator, Simulation, Connecting Modules) (checkoff by 9/24) HW 2 (due 9/20) HW 2 solution
  9/11 Verilog II slides webcast        
4 9/16 Combinational Logic slides webcast Discussion 4 (K-Maps, Logic Minimization, FSMs) Lab 4 (Floorplanning, Placement, and Power) Lab 4 (ROMs and IO Circuits) (checkoff by 10/8) HW 3 (due 9/27) HW 3 solution
  9/18 FSMs slides webcast        
5 9/23 FSMs 2 slides webcast Discussion 5 (RISC-V ISA, Datapath, Decoder) No new lab this week No new lab this week HW 4 (due 10/4) HW 4 solution
9/25 RISC-V Datapath and Control slides webcast
6 9/30 RISC-V Pipelining slides webcast Discussion 6 (RISC-V ISA, Pipelining, Hazards) Lab 5 (Parallelization and Routing) (due 10/18) Lab 5 (FSMs and UART) (checkoff by 10/17) HW 5 (due 10/12) HW 5 solution
10/2 Midterm 1 (A Solution, B Solution)
7 10/7 FPGA slides No discussion on Friday (10/11)
Monday Discussion (10/14)
No new lab this week No new lab this week No new HW
10/9 No lecture
8 10/14 CMOS slides Discussion 8 (Pipeline Hazards, MOS Switch Model, CMOS Logic) Lab 6 (SRAM Integration and Post-PAR Simulation) (due 10/25) Lab 6 (FIFOs, UART Piano) (checkoff by 10/24) HW 6 (due 10/25) HW 6 solution
10/16 CMOS Gate Construction, Sizing, Inverter Delay slides
9 10/21 Delay slides Discussion 9 (MOS Switch, VTCs, CMOS, Sizing, RC Delay, Logical EFfort) ASIC Project Spec (Checkpoint 1) (due 11/08) FPGA Project (Checkpoint 1 due 11/1) HW 7 (due 11/03) HW 7 solution
10/23 Wires and Energy slides ASIC Project Spec (Checkpoint 2) (due 11/22)
10 10/28 No lecture Discussion 10 (Gate Sizing, RC Delay, Logical Effort, Power/Energy, Adders) Checkpoint 1 due Friday, 11/8 Checkpoint 1 due Friday, 11/1 HW 8 (due 11/08) HW 8 Solution
10/30 Adders slides
Multipliers (recorded) slides
11 11/4 Flip-Flops slides Discussion 11 (Adders, Midterm 2) Checkpoint 2 due Friday, 11/22 Checkpoint 2 due Friday, 11/22 No homework
11/6 Midterm 2 (Solution)
12 11/11 Veteran's Day Discussion 12 (Multipliers, Timing, Latches/FFs, SRAMs) ASIC Project Spec (Checkpoint 3) (due 11/29) Checkpoint 2 due Friday, 11/22 HW 9 (due 11/25) HW 9 Solution
11/13 SRAM slides
13 11/18 Caches slides Discussion 13 (Timing, Latches/FFs, SRAMs, Caches)
11/20 Memory and Clocking slides
14 11/25 Flash and Parallelism slides HW 10 (due 12/6) HW 10 Solution
11/27 Thanksgiving Holiday
15 12/2 Power Distribution slides Discussion 14 (Caches, FIFOs, DRAM, Parallelism/Pipelining) ASIC Project Spec (Checkpoint 4) (due 12/11)
12/4 Summary slides

Resources

Textbooks

Verilog

Protocols & Standards

Staff

bora photo Borivoje Nikolic bora at berkeley dot edu
sophia photo Sophia Shao ysshao at berkeley dot edu
vighnesh photo Vighnesh Iyer vighnesh.iyer at berkeley dot edu
Rebekah Zhao rebekah_zhao at berkeley dot edu
ryan photo Ryan Kaveh ryankaveh at berkeley dot edu
cem photo Cem Yalcin cemyalcin at berkeley dot edu

Grading

Class

Problem Sets 20%
Midterm Exam 1 20%
Midterm Exam 2 20%
Final Exam 40%

ASIC Labs

Lab Reports 37.5%
Project 62.5%

FPGA Labs

Lab Checkoffs 25%
Project 75%

Cheating Policy

  • If you turn in someone else’s work as if it were your own, you are guilty of cheating.  This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
  • Also, if you knowingly aid in cheating, you are guilty.
  • We have software that compares your submitted work to others.
  • However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
  • Do not post your work on public repositories like github (private o.k.)
  • If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat!  
If it is a midterm exam, final exam, or final project, you get an F in the class.  All cases of cheating reported to the office of student conduct.