Course Outline

Week Date Lecture Topic Recording Optional reading Discussion ASIC Lab FPGA Lab Homework Homework Solution
1 08/25 Class Organization and Introduction slides recording No Reading No Discussion No ASIC Lab No FPGA Lab No Homework
2 08/30 Design Abstraction slides recording No Reading Discussion 1 (slides) (recording) Lab 1 Lab 1 Homework 1 Solutions
09/01 Metrics and Verilog I slides recording RCN: 1.3, H&H:4.1-4.2
3 09/06 Verilog II slides recording H&H:4.3-4.5 Discussion 2 (slides) (recording)
4 states of verilog signals
Lab 2 Lab 2 Homework 2 Solutions
09/08 Combinational Logic I slides recording H&H:2.1-2.4
4 09/13 Combinational Logic II + FSM slides recording H&H:2.7,3.1,3.4 Discussion 3 (slides) (recording) Lab 3 Lab 3 Homework 3 Solutions
09/15 FSM II + RISC-V Intro slides recording P&H:2.1-2.4
5 09/20 RISC-V Datapath I slides recording P&H:2.7-2.10 Discussion 4 (slides) (recording) Lab 4 Lab 4 Homework 4 Solutions
09/22 RISC-V Datapath II slides recording H&H:6.4,7.3
6 09/27 RISC-V Pipelining slides recording H&H:7.5 Discussion 5 (slides) (recording) Homework 5 Solutions
09/29 FPGA slides recording N/A
7 10/04 Guest Lecture: FPGA Emulation N/A Discussion 6 (blank slides) (annotated) (recording) Lab 5 Lab 5 No Homework!
10/06 CMOS slides recording RCN 3.3.1-2, 6.2.1
8 10/11 Inverter Delay slides recording RCN 5.1-2, 5.4.2 Discussion 7 (slides) (recording) Homework 6 Solutions
10/13 Inverter Chain Delay slides recording W&H: 4.4-4.5
9 10/18 Logical Effort slides recording W&H: 4.4-4.5 Discussion 7 (slides) (recording) Lab 6 FPGA Project
10/20 No Lecture.
10 10/25 Midterm recording (midterm review) (recording: Q1 & Q3) (recording: Q4) ASIC Project Midterm Solutions
10/27 Guest Lecture on Verification
11 11/1 Wire and Energy slides recording W&H: 6.1-6.3.1, 5.1-5.3 Discussion 8 + Elmore delay (slides) (recording)
11/3 Adders slides recording RCN: 11.3 Homework 7 Solutions
12 11/8 Adders and Multipliers slides recording RCN: 11.4 Sp22 Adder Discussion (blank slides) (annotated slides) (recording)
11/10 Multipliers II slides recording RCN: 11.4 Sp22 Multiplier Discussion (blank slides) (annotated slides) (recording) Homework 8
13 11/15 FlipFlops slides recording RCN: 7.1-7.3
11/17 FlipFlops II + SRAM slides recording RCN: 12.2.3 Sp22 FlipFlops + SRAM Discussion (blank slides) (annotated slides) recording
14 11/22 SRAM II slides recording RCN: 12.3.1
11/24 Thanksgiving Homework 9
15 11/29 Summary slides recording
12/1 Guest Lecture: SystemVerilog slides

Lectures, Labs, Office Hours



Click to open the queue for Labs and Office Hours

Homework

  • Ask questions on our Ed Discussion forum.
  • Homeworks will be posted as links in the outline above. Please submit completed homework via Gradescope. See Ed Discussion for the entry code.
  • Homework will be released on Thursdays before midnight, and will be due next Friday 8 days later. Homework will be challenging and graded for correctness.

Exams

Resources

Textbooks

Verilog

Protocols & Standards

CS61C videos

Staff

Sophia photo Sophia Shao ysshao at berkeley dot edu
Yikuan Chen chenyikuan110 at berkeley dot edu
Erik photo Erik Anderson erik dot f dot anderson at berkeley dot edu
Simon Guo Simon Guo simonguozirui at berkeley dot edu
Hansung Kim Hansung Kim hansung_kim at berkeley dot edu
Paul photo Paul Kwon hyunjaekwon at berkeley dot edu
Roger photo Roger Hsiao roger_hsiao at berkeley dot edu
Richard Yan Richard Yan yrh at berkeley dot edu
Ella Schwarz Ella Schwarz schwarzem at berkeley dot edu
Jennifer Zhou Jennifer Zhou jennifersiyuanzhou at berkeley dot edu
Raghav Gupta Raghav Gupta raghavgupta at berkeley dot edu
Simon Guo Chengyi Zhang (Reader) iansseijelly at berkeley dot edu

Grading

Class

Problem Sets 30%
Midterm 30%
Final Exam 40%

ASIC Labs

Lab Reports 37.5%
Project 62.5%

FPGA Labs

Lab Checkoffs 25%
Project 75%

Honor Code

  • If you turn in someone else’s work as if it were your own, you are guilty of cheating.  This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
  • Also, if you knowingly aid in cheating, you are guilty.
  • We have software that compares your submitted work to others.
  • However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
  • Do not post your work on public repositories like github (private o.k.)
  • If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat!  If it is a midterm exam, final exam, or final project, you get an F in the class.  All cases of cheating reported to the office of student conduct.