1 |
8/28 |
Class Organization & Introduction to Course Content
slides
webcast
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Discussion 1 (Intro) |
Lab 1 (Getting Around the Compute Environment) |
Lab 1 (Setup Accounts, Verilog Intro, FPGA Basics) |
No homework! |
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2 |
9/4 |
Design Process
slides
webcast |
Discussion 2 (Noise Margins, Verilog, Simulation) code |
Lab 2 (Simulation) |
Lab 2 (Introduction to FPGA Development) |
HW 1 |
HW 1 solution |
3 |
9/9 |
Verilog I
slides
webcast
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Discussion 3 (Verilog Simulation, Parameterized Modules) code |
Lab 3 (Logic Synthesis) |
Lab 3 (Tone Generator, Simulation, Connecting Modules) (checkoff by 9/24) |
HW 2 (due 9/20) |
HW 2 solution |
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9/11 |
Verilog II
slides
webcast |
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4 |
9/16 |
Combinational Logic
slides
webcast |
Discussion 4 (K-Maps, Logic Minimization, FSMs) |
Lab 4 (Floorplanning, Placement, and Power) |
Lab 4 (ROMs and IO Circuits) (checkoff by 10/8) |
HW 3 (due 9/27) |
HW 3 solution |
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9/18 |
FSMs
slides
webcast |
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5 |
9/23 |
FSMs 2
slides
webcast
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Discussion 5 (RISC-V ISA, Datapath, Decoder) |
No new lab this week |
No new lab this week |
HW 4 (due 10/4) |
HW 4 solution |
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9/25 |
RISC-V Datapath and Control
slides
webcast
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6 |
9/30 |
RISC-V Pipelining
slides
webcast
| Discussion 6 (RISC-V ISA, Pipelining, Hazards) |
Lab 5 (Parallelization and Routing) (due 10/18) |
Lab 5 (FSMs and UART) (checkoff by 10/17) |
HW 5 (due 10/12) |
HW 5 solution |
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10/2 |
Midterm 1 (A Solution, B Solution) |
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7 |
10/7 |
FPGA
slides
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No discussion on Friday (10/11)
Monday Discussion (10/14)
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No new lab this week |
No new lab this week |
No new HW |
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10/9 |
No lecture |
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8 |
10/14 |
CMOS slides |
Discussion 8 (Pipeline Hazards, MOS Switch Model, CMOS Logic) |
Lab 6 (SRAM Integration and Post-PAR Simulation) (due 10/25) |
Lab 6 (FIFOs, UART Piano) (checkoff by 10/24) |
HW 6 (due 10/25) |
HW 6 solution |
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10/16 |
CMOS Gate Construction, Sizing, Inverter Delay slides |
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9 |
10/21 |
Delay slides |
Discussion 9 (MOS Switch, VTCs, CMOS, Sizing, RC Delay, Logical EFfort) |
ASIC Project Spec (Checkpoint 1) (due 11/08) |
FPGA Project (Checkpoint 1 due 11/1) |
HW 7 (due 11/03) |
HW 7 solution |
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10/23 |
Wires and Energy slides |
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ASIC Project Spec (Checkpoint 2) (due 11/22) |
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10 |
10/28 |
No lecture |
Discussion 10 (Gate Sizing, RC Delay, Logical Effort, Power/Energy, Adders) |
Checkpoint 1 due Friday, 11/8 |
Checkpoint 1 due Friday, 11/1 |
HW 8 (due 11/08) |
HW 8 Solution |
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10/30 |
Adders slides
Multipliers (recorded) slides
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11 |
11/4 |
Flip-Flops slides |
Discussion 11 (Adders, Midterm 2) |
Checkpoint 2 due Friday, 11/22 |
Checkpoint 2 due Friday, 11/22 |
No homework |
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11/6 |
Midterm 2 (Solution) |
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12 |
11/11 |
Veteran's Day |
Discussion 12 (Multipliers, Timing, Latches/FFs, SRAMs) |
ASIC Project Spec (Checkpoint 3) (due 11/29) |
Checkpoint 2 due Friday, 11/22 |
HW 9 (due 11/25) |
HW 9 Solution |
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11/13 |
SRAM slides |
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13 |
11/18 |
Caches slides |
Discussion 13 (Timing, Latches/FFs, SRAMs, Caches) |
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11/20 |
Memory and Clocking slides |
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14 |
11/25 |
Flash and Parallelism slides |
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HW 10 (due 12/6) |
HW 10 Solution |
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11/27 |
Thanksgiving Holiday |
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15 |
12/2 |
Power Distribution slides |
Discussion 14 (Caches, FIFOs, DRAM, Parallelism/Pipelining) |
ASIC Project Spec (Checkpoint 4) (due 12/11) |
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12/4 |
Summary slides |
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