University of California, Berkeley

Electrical Engineering and Computer Sciences Department

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Fall 2019 Lecture Notes:

In case lecture listed below cannot be conducted on schedule, appropriate arrangements for the lecture will be made. These will likely entail make-up lectures, possibly in the evenings.
Lec No. Date Topics Files/Links Reading Homework Lab
1 08/28
  • Administrative Info
  • Intro/Overview: What is 140 all about?
W1L1
  • Razavi: Ch 1, Ch 2.1-2.3
  • GLHM: Page xiv symbol conventions
  • GLHM: 1.5, 1.6 MOS large & small signal models
  • GLHM: Skim Ch 3
HW 1
2 08/30
  • Op amp circuits circuits in Lab 1
W1L2
  • See Lec 1
HW 1 Lab 1
3 09/04
  • Diode, BJT, and MOS physics
W2L1
  • Razavi: Ch 2.4-2.6
  • Razavi: Skim 2.5 & 2.6
  • GLHM: Ch 1.2
HW 2
4 09/04
  • Diode, BJT, and MOS physics
  • MOS small signal model
W2L2
Taylor
Heaviside
Bode
  • See Lec 3
HW 2
5 09/11
  • Small signal model
W3L1
  • Razavi: Ch-3.1-3.4 (esp. figures 3.5, 3.6, 3.18-3.20)
  • Razavi: Ch-6.2 through eqn 6.22
  • GLHM: Ch-7.1, 7.2.1 up through eqn.7.27
  • GLHM: Ch-3.1, 3.2, 3.3.2
HW 3 Lab 2
6 09/13
  • Common source amplifiers
  • Single-pole amplifiers
  • Frequency response
W3L2
  • See Lec 5
HW 3 Lab 2
7 09/18
  • Poles/zeros
  • Step response
  • Common source amplifier (active load)
W4L1
  • GLHM: 3.3.5 (eqns. 3.55 and 66)
  • GLHM: 3.4.2.2 (eqns 3.126, 127, 128) Figure 4.17
HW 4 Lab 3 (Part 1)
8 09/20
  • Common source amplifier (active load)
  • CS design
W4L2
  • See Lec 7
HW 4 Lab 3 (Part 1)
9 09/25
  • RESCHEDULED
W5L1 Video
    Lab 3 (Part 1)
    10 09/27
    • Midterm 1
    Midterm 1 Solution
      Lab 3 (Part 1)
      11 10/02
      • 2-stage op amp
      • Current mirrors
      W6L1
      • Razavi: Ch-6.2
      • Razavi: Ch-10.1-10.6
      • GLHM: Ch-6 read 6.1.1, skim through eqn 6.25
      • GLHM: Ch-6.3 through 6.3.5 inclusive
      • GLHM: 8 through 8.2 inclusive 9.1,2
      HW 5 Lab 3 (Part 1)
      12 10/04
      • 2-stage op amp
      • Current mirrors
      • Feedback
      W6L2
      • See Lec 11
      HW 5 Lab 3 (Part 1)
      13 10/15
      • Gain error
      • Bode plots
      • S-domain
      • Feedback
      W7L1
      W7L1 Video
      • Razavi: Ch-5.3 (esp. figures 5.23, 5.29 and 5.3)}
      • GLHM: Ch-9.3 through 9.4.3 inclusive
      HW 6 Lab 3 (Part 2)
      14 10/16
      • Multi-pole systems
      • S-domain
      W7L2
      • See Lecture 13
      HW 6 Lab 3 (Part 2)
      15 10/17
      • 2-stage amplifier
      • Multi-pole systems
      • Compensation
      W7L3
      • GLHM: 4.4.2, 4.4.3 biasing; emphasis on the MOS parts
      HW 6 Lab 3 (Part 2)
      16 10/18
      • 2-stage amplifier
      • Compensation
      • RHP zero
      • Current mirror PZ doublet
      W7L4
      W7L4 (TA)
        HW 6/7 Lab 3 (Part 2)
        17 10/23
        • 2-stage amplifier
        • poles and zeros
        • Common mode gain
        • slew rate
        • Current mirror op amp
        W9L1
          HW 7 Lab 4
          18 10/25
          • Supply-independent biasing
          • Bandgap
          • Temperature sensor
          W9L2
          • GLHM: 4.4.2, 4.4.3 biasing; emphasis on the MOS parts
          HW 8 Lab 4
          19 10/30
          • Bandgap
          • Temperature sensor
          • Cascode
          W10L1
            Lab 4
            20 11/01
            • Midterm 2
            Midterm 2 Solution
              Lab 4
              21 11/06
              • Telescopic cascode
              • Folded cascode
              • High swing biasing
              • Switched caps
              W11L1
              • GLHM: Ch-6.1.7.1 Switched capacitor amplifier
              • GLHM: 6.6 folded cascode
              • Razavi: Ch-5.1-5.2
              • Razavi: Ch-9.2
              HW 9 Lab 4/5
              22 11/08
              • Switched caps
              • Capacitor biases
              • Settling
              • PGA
              • Switches
              W11L2
              • Razavi: Ch-13.2
              • GLHM: Ch-4.2.5.2 high swing current mirrors
              HW 9 Lab 4/5
              23 11/13
              • Design
              • Analog mux
              • Regulators
              • Cap DAC, ADC
              W12L1
                Lab 4/5
                24 11/15
                • SAR ADCs
                • PGA driving to ground
                W12L2
                  HW 10 Lab 4/5
                  25 11/20
                  • PGA, continued
                  • Switches and charge injection
                  • Comparators: StrongARM Latch
                  W13L1
                  StrongARM Latch
                    HW 10 Lab 5
                    26 11/22
                    • Digital circuits
                    • Flip flops
                    • Digital current
                    • Regulators
                    • PGA gain, gain error
                    • C program interface
                    W13L2
                      Lab 5, Project
                      Last updated 2019-11-22 14:07