Lectures and Office Hours

Lectures Tues, Thurs 9:30 am - 11:00 am Cory 521 Borivoje Nikolic
Discussion Fri 9:00 am - 10:00 am Cory 521 Rohan Kumar
Office Hours Thurs 11:00 am - 12:00 pm Cory 509 Borivoje Nikolic
Thursday 3:30 pm - 4:30 pm Berkeley Wireless Research Center Rohan Kumar

Homework

  • Homeworks will be posted as links in the outline below.
  • Ask questions on our Ed Discussion forum.

Exams

  • There will be four quizzes during the semester.
  • Final exam will be held during the last week of the course.

Course Outline

Class Date Lecture Topic Quiz Reading Lab Homework Discussion
1 1/16 Intro slides Moore03, Chen06
2 1/18 Chipyard slides Amid20, Dennard74, UCIe white paper Lab 1 (due 1/26) Discussion 1 recording slides
3 1/23 Design Productivity slides Chisel Bootcamp
4 1/25 SystemVerilog slides Lab 2 (due 2/2) Homework 1 (solution) Discussion 2 recording slides
5 1/30 System Interconnect I slides
6 2/1 System Interconnect II slides Lab 3 (due 2/9) Discussion 3 recording slides
7 2/6 RoCC & TileLink slides
8 2/8 TileLink & Modern Technology slides Lab 4A (due 2/16) Discussion 4 slides
9 2/13 Implications of Lithography slides
10 2/15 Technology (Part 2) slides Lab 4B (due 2/23) Homework 2 (solution) Discussion 5 recording slides
11 2/22 Transistor Models slides Sodini84, Toh88, Sakurai90 Discussion 6 recording slides
12 2/27 Standard Cells slides Quiz 1 (solution)
13 3/1 Delay Models slides
14 3/5 Timing slides
15 3/7 Latches and FFs slides Partovi01 Homework 3 (solution)
16 3/12 Variability slides Quiz 2 (solution) Bernstein06
17 3/14 Variability slides Discussion 7 recording slides annotated
18 3/16 SRAM Guest Lecture Amrutur98 Niki11 Osada04
19 3/21 SRAM Peripherals slides
20  4/2 Power-Performance Tradeoffs slides
21 4/4 Low-Power Design slides Quiz 3 (solution) Zyuban04 Chandrakasan95 Rabaey Ch.4 Lab 5 (due 4/12) Homework 4 (solution) Discussion 8 recording slides annotated
22 4/8 Preliminary design reviews Burd00
23 4/11 DVFS slides
24 4/16 Multiple Thresholds, Sleep Modes slides Quiz 4 (solution)
25 4/18 Clock Generation, PLLs slides Homework 5 (solution) Discussion 9 recording slides annotated
26 4/23 Supply slides Wong06
27 4/25 Final Exam

Resources

Textbooks

  • Baseline Low Power Design Essentials, J. Rabaey, Springer, 2009.
  • Useful Digital Integrated Circuits: A Design Perspective, Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolić
  • Useful CMOS VLSI Design, Neil Weste, David Harris
  • Useful Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE Press, 2001.
  • Useful VLSI Design Methodology Development, T. Dillinger, Pearson, 2019.

Staff

bora photo Borivoje Nikolic bora at berkeley dot edu
rohan photo Rohan Kumar eecs251b at berkeley dot edu
elam photo Elam Day-Friedland eecs251b at berkeley dot edu
elam photo Daniel Kramnik eecs251b at berkeley dot edu

Grading

Assignments 20%
Design Project 40%
Quizzes 10%
Final Exam 30%

Cheating Policy

  • If you turn in someone else’s work as if it were your own, you are guilty of cheating.  This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
  • Also, if you knowingly aid in cheating, you are guilty.
  • We have software that compares your submitted work to others.
  • However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
  • Do not post your work on public repositories like github (private o.k.)
  • If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat!  If it is a midterm exam, final exam, or final project, you get an F in the class.  All cases of cheating reported to the office of student conduct.